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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 15:49:37.0867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eb96423-b5a4-400e-e827-08de1c82ec84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6072 Received-SPF: permerror client-ip=2a01:111:f403:c001::2; envelope-from=skolothumtho@nvidia.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1762357860756158501 Install an event handler on the vEVENTQ fd to read and propagate host generated vIOMMU events to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 62 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 2 ++ 2 files changed, 64 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 210e7ebf36..e6c81c4786 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -383,6 +383,62 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUSta= te *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static void smmuv3_accel_event_read(void *opaque) +{ + SMMUv3State *s =3D opaque; + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUViommu *vsmmu =3D s_accel->vsmmu; + struct iommu_vevent_arm_smmuv3 *vevent; + struct iommufd_vevent_header *hdr; + ssize_t readsz =3D sizeof(*hdr) + sizeof(*vevent); + uint8_t buf[sizeof(*hdr) + sizeof(*vevent)]; + uint32_t last_seq =3D vsmmu->last_event_seq; + ssize_t bytes; + Evt evt =3D {}; + + bytes =3D read(vsmmu->veventq->veventq_fd, buf, readsz); + if (bytes <=3D 0) { + if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { + return; + } + error_report("vEVENTQ: read failed (%s)", strerror(errno)); + return; + } + + if (bytes < readsz) { + error_report("vEVENTQ: incomplete read (%zd/%zd bytes)", bytes, re= adsz); + return; + } + + hdr =3D (struct iommufd_vevent_header *)buf; + if (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS) { + error_report("vEVENTQ has lost events"); + return; + } + + vevent =3D (struct iommu_vevent_arm_smmuv3 *)(buf + sizeof(*hdr)); + /* Check sequence in hdr for lost events if any */ + if (vsmmu->event_start) { + uint32_t expected =3D (last_seq =3D=3D INT_MAX) ? 0 : last_seq + 1; + + if (hdr->sequence !=3D expected) { + uint32_t delta; + + if (hdr->sequence >=3D last_seq) { + delta =3D hdr->sequence - last_seq; + } else { + /* Handle wraparound from INT_MAX */ + delta =3D (INT_MAX - last_seq) + hdr->sequence + 1; + } + error_report("vEVENTQ: detected lost %u event(s)", delta - 1); + } + } + vsmmu->last_event_seq =3D hdr->sequence; + vsmmu->event_start =3D true; + memcpy(&evt, vevent, sizeof(evt)); + smmuv3_propagate_event(s, &evt); +} + static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) { IOMMUFDVeventq *veventq =3D vsmmu->veventq; @@ -390,6 +446,8 @@ static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) if (!veventq) { return; } + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); + close(veventq->veventq_fd); iommufd_backend_free_id(vsmmu->iommufd, veventq->veventq_id); g_free(veventq); vsmmu->veventq =3D NULL; @@ -433,6 +491,10 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error = **errp) veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D &vsmmu->viommu; vsmmu->veventq =3D veventq; + + /* Set up event handler for veventq fd */ + fcntl(veventq_fd, F_SETFL, O_NONBLOCK); + qemu_set_fd_handler(veventq_fd, smmuv3_accel_event_read, NULL, s); return true; } =20 diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 740253bc34..6ed5f3b821 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -23,6 +23,8 @@ typedef struct SMMUViommu { IOMMUFDBackend *iommufd; IOMMUFDViommu viommu; IOMMUFDVeventq *veventq; + uint32_t last_event_seq; + bool event_start; uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; --=20 2.43.0