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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 15:49:28.7546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f1e0233-81a7-40b0-33db-08de1c82e778 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6178 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1762357856803158500 From: Nicolin Chen When the guest enables the Event Queue and a vIOMMU is present, allocate a vEVENTQ object so that host-side events related to the vIOMMU can be received and propagated back to the guest. For cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created before the guest boots. In this case, the vEVENTQ is allocated when the guest writes to SMMU_CR0 and sets EVENTQEN =3D 1. If no cold-plugged device exists at boot (i.e. no vIOMMU initially), the vEVENTQ is allocated when a vIOMMU is created, i.e. during the first device hot-plug. Event read and propagation will be added in a later patch. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 6 +++++ hw/arm/smmuv3.c | 7 +++++ 3 files changed, 74 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1f206be8e4..210e7ebf36 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -383,6 +383,59 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUSta= te *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) +{ + IOMMUFDVeventq *veventq =3D vsmmu->veventq; + + if (!veventq) { + return; + } + iommufd_backend_free_id(vsmmu->iommufd, veventq->veventq_id); + g_free(veventq); + vsmmu->veventq =3D NULL; +} + +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + IOMMUFDVeventq *veventq; + SMMUViommu *vsmmu; + uint32_t veventq_id; + uint32_t veventq_fd; + + if (!s_accel || !s_accel->vsmmu) { + return true; + } + + vsmmu =3D s_accel->vsmmu; + if (vsmmu->veventq) { + return true; + } + + /* + * Check whether the Guest has enabled the Event Queue. The queue enab= led + * means EVENTQ_BASE has been programmed with a valid base address and= size. + * If it=E2=80=99s not yet configured, return and retry later. + */ + if (!smmuv3_eventq_enabled(s)) { + return true; + } + + if (!iommufd_backend_alloc_veventq(vsmmu->iommufd, vsmmu->viommu.viomm= u_id, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, + 1 << s->eventq.log2size, &veventq_i= d, + &veventq_fd, errp)) { + return false; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + veventq->viommu =3D &vsmmu->viommu; + vsmmu->veventq =3D veventq; + return true; +} + static bool smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, HostIOMMUDeviceIOMMUFD *idev, Error **errp) @@ -438,8 +491,15 @@ smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel= _dev, vsmmu->iommufd =3D idev->iommufd; s_accel->vsmmu =3D vsmmu; accel_dev->vsmmu =3D vsmmu; + + /* Allocate a vEVENTQ if guest has enabled event queue */ + if (!smmuv3_accel_alloc_veventq(s, errp)) { + goto free_bypass_hwpt; + } return true; =20 +free_bypass_hwpt: + iommufd_backend_free_id(idev->iommufd, vsmmu->bypass_hwpt_id); free_abort_hwpt: iommufd_backend_free_id(idev->iommufd, vsmmu->abort_hwpt_id); free_viommu: @@ -536,6 +596,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, } =20 if (QLIST_EMPTY(&vsmmu->device_list)) { + smmuv3_accel_free_veventq(vsmmu); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->bypass_hwpt_id); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->abort_hwpt_id); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->viommu.viommu_id); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 4f5b672712..740253bc34 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -22,6 +22,7 @@ typedef struct SMMUViommu { IOMMUFDBackend *iommufd; IOMMUFDViommu viommu; + IOMMUFDVeventq *veventq; uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; @@ -56,6 +57,7 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, void smmuv3_accel_gbpa_update(SMMUv3State *s); void smmuv3_accel_reset(SMMUv3State *s); void smmuv3_accel_idr_override(SMMUv3State *s); +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -87,6 +89,10 @@ static inline void smmuv3_accel_reset(SMMUv3State *s) static inline void smmuv3_accel_idr_override(SMMUv3State *s) { } +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e1140fe087..976a436bd4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1616,12 +1616,19 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwa= ddr offset, static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + Error *local_err =3D NULL; + switch (offset) { case A_CR0: s->cr[0] =3D data; s->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ smmuv3_cmdq_consume(s); + /* Allocate vEVENTQ if guest enables EventQ and vIOMMU is ready */ + if (!smmuv3_accel_alloc_veventq(s, &local_err)) { + error_report_err(local_err); + /* TODO: Should we return err? */ + } return MEMTX_OK; case A_CR1: s->cr[1] =3D data; --=20 2.43.0