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charset="utf-8" From: Nicolin Chen Add a new helper for IOMMU_VEVENTQ_ALLOC ioctl to allocate a virtual event queue (vEVENTQ) for a vIOMMU object. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 31 +++++++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 12 ++++++++++++ 3 files changed, 44 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 392f9cf2a8..4a6aebdb42 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -503,6 +503,37 @@ bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, ui= nt32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t type, uint32_t depth, + uint32_t *out_veventq_id, + uint32_t *out_veventq_fd, Error **errp) +{ + int ret; + struct iommu_veventq_alloc alloc_veventq =3D { + .size =3D sizeof(alloc_veventq), + .flags =3D 0, + .type =3D type, + .veventq_depth =3D depth, + .viommu_id =3D viommu_id, + }; + + ret =3D ioctl(be->fd, IOMMU_VEVENTQ_ALLOC, &alloc_veventq); + + trace_iommufd_viommu_alloc_eventq(be->fd, viommu_id, type, + alloc_veventq.out_veventq_id, + alloc_veventq.out_veventq_fd, ret); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VEVENTQ_ALLOC failed"); + return false; + } + + g_assert(out_veventq_id); + g_assert(out_veventq_fd); + *out_veventq_id =3D alloc_veventq.out_veventq_id; + *out_veventq_fd =3D alloc_veventq.out_veventq_fd; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 8408dc8701..5afa7a40be 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -23,3 +23,4 @@ iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hw= pt_id, uint64_t iova, u iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" +iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index aa78bf1e1d..9770ff1484 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -56,6 +56,13 @@ typedef struct IOMMUFDVdev { uint32_t virt_id; /* virtual device ID */ } IOMMUFDVdev; =20 +/* Virtual event queue interface for a vIOMMU */ +typedef struct IOMMUFDVeventq { + IOMMUFDViommu *viommu; + uint32_t veventq_id; + uint32_t veventq_fd; +} IOMMUFDVeventq; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -86,6 +93,11 @@ bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint= 32_t dev_id, uint32_t viommu_id, uint64_t virt_id, uint32_t *out_vdev_id, Error **errp); =20 +bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t type, uint32_t depth, + uint32_t *out_veventq_id, + uint32_t *out_veventq_fd, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Fri Nov 14 15:21:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 15:49:28.7546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f1e0233-81a7-40b0-33db-08de1c82e778 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6178 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1762357856803158500 From: Nicolin Chen When the guest enables the Event Queue and a vIOMMU is present, allocate a vEVENTQ object so that host-side events related to the vIOMMU can be received and propagated back to the guest. For cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created before the guest boots. In this case, the vEVENTQ is allocated when the guest writes to SMMU_CR0 and sets EVENTQEN =3D 1. If no cold-plugged device exists at boot (i.e. no vIOMMU initially), the vEVENTQ is allocated when a vIOMMU is created, i.e. during the first device hot-plug. Event read and propagation will be added in a later patch. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 6 +++++ hw/arm/smmuv3.c | 7 +++++ 3 files changed, 74 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1f206be8e4..210e7ebf36 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -383,6 +383,59 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUSta= te *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) +{ + IOMMUFDVeventq *veventq =3D vsmmu->veventq; + + if (!veventq) { + return; + } + iommufd_backend_free_id(vsmmu->iommufd, veventq->veventq_id); + g_free(veventq); + vsmmu->veventq =3D NULL; +} + +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + IOMMUFDVeventq *veventq; + SMMUViommu *vsmmu; + uint32_t veventq_id; + uint32_t veventq_fd; + + if (!s_accel || !s_accel->vsmmu) { + return true; + } + + vsmmu =3D s_accel->vsmmu; + if (vsmmu->veventq) { + return true; + } + + /* + * Check whether the Guest has enabled the Event Queue. The queue enab= led + * means EVENTQ_BASE has been programmed with a valid base address and= size. + * If it=E2=80=99s not yet configured, return and retry later. + */ + if (!smmuv3_eventq_enabled(s)) { + return true; + } + + if (!iommufd_backend_alloc_veventq(vsmmu->iommufd, vsmmu->viommu.viomm= u_id, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, + 1 << s->eventq.log2size, &veventq_i= d, + &veventq_fd, errp)) { + return false; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + veventq->viommu =3D &vsmmu->viommu; + vsmmu->veventq =3D veventq; + return true; +} + static bool smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, HostIOMMUDeviceIOMMUFD *idev, Error **errp) @@ -438,8 +491,15 @@ smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel= _dev, vsmmu->iommufd =3D idev->iommufd; s_accel->vsmmu =3D vsmmu; accel_dev->vsmmu =3D vsmmu; + + /* Allocate a vEVENTQ if guest has enabled event queue */ + if (!smmuv3_accel_alloc_veventq(s, errp)) { + goto free_bypass_hwpt; + } return true; =20 +free_bypass_hwpt: + iommufd_backend_free_id(idev->iommufd, vsmmu->bypass_hwpt_id); free_abort_hwpt: iommufd_backend_free_id(idev->iommufd, vsmmu->abort_hwpt_id); free_viommu: @@ -536,6 +596,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, } =20 if (QLIST_EMPTY(&vsmmu->device_list)) { + smmuv3_accel_free_veventq(vsmmu); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->bypass_hwpt_id); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->abort_hwpt_id); iommufd_backend_free_id(vsmmu->iommufd, vsmmu->viommu.viommu_id); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 4f5b672712..740253bc34 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -22,6 +22,7 @@ typedef struct SMMUViommu { IOMMUFDBackend *iommufd; IOMMUFDViommu viommu; + IOMMUFDVeventq *veventq; uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; @@ -56,6 +57,7 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, void smmuv3_accel_gbpa_update(SMMUv3State *s); void smmuv3_accel_reset(SMMUv3State *s); void smmuv3_accel_idr_override(SMMUv3State *s); +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -87,6 +89,10 @@ static inline void smmuv3_accel_reset(SMMUv3State *s) static inline void smmuv3_accel_idr_override(SMMUv3State *s) { } +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e1140fe087..976a436bd4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1616,12 +1616,19 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwa= ddr offset, static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + Error *local_err =3D NULL; + switch (offset) { case A_CR0: s->cr[0] =3D data; s->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ smmuv3_cmdq_consume(s); + /* Allocate vEVENTQ if guest enables EventQ and vIOMMU is ready */ + if (!smmuv3_accel_alloc_veventq(s, &local_err)) { + error_report_err(local_err); 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charset="utf-8" Factor out the code that propagates event records to the guest into a helper function. The accelerated SMMUv3 path can use this to propagate host events in a subsequent patch. Since this helper may be called from outside the SMMUv3 core, take the mutex before accessing the Event Queue. No functional change intended. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-internal.h | 4 ++++ hw/arm/smmuv3.c | 21 +++++++++++++++------ hw/arm/trace-events | 2 +- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 2e0d8d538b..58dfa64eb3 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -525,7 +525,11 @@ typedef struct SMMUEventInfo { (x)->word[6] =3D (uint32_t)(addr & 0xffffffff); \ } while (0) =20 +#define EVT_GET_TYPE(x) extract32((x)->word[0], 0, 8) +#define EVT_GET_SID(x) ((x)->word[1]) + void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); +void smmuv3_propagate_event(SMMUv3State *s, Evt *evt); =20 /* Configuration Data */ =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 976a436bd4..43d297698b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -168,10 +168,23 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s= , Evt *evt) return MEMTX_OK; } =20 +void smmuv3_propagate_event(SMMUv3State *s, Evt *evt) +{ + MemTxResult r; + + trace_smmuv3_propagate_event(smmu_event_string(EVT_GET_TYPE(evt)), + EVT_GET_SID(evt)); + qemu_mutex_lock(&s->mutex); + r =3D smmuv3_write_eventq(s, evt); + if (r !=3D MEMTX_OK) { + smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MAS= K); + } + qemu_mutex_unlock(&s->mutex); +} + void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) { Evt evt =3D {}; - MemTxResult r; =20 if (!smmuv3_eventq_enabled(s)) { return; @@ -251,11 +264,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo= *info) g_assert_not_reached(); } =20 - trace_smmuv3_record_event(smmu_event_string(info->type), info->sid); - r =3D smmuv3_write_eventq(s, &evt); - if (r !=3D MEMTX_OK) { - smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MAS= K); - } + smmuv3_propagate_event(s, &evt); info->recorded =3D true; } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2e0b1f8f6f..bbe989d042 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -40,7 +40,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, u= int8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error = on %s command execution: %d" smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) = "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" -smmuv3_record_event(const char *type, uint32_t sid) "%s sid=3D0x%x" +smmuv3_propagate_event(const char *type, uint32_t sid) "%s sid=3D0x%x" smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid= =3D0x%x features:0x%x, sid_split:0x%x" smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offs= et, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRI= x64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_st= e:%d" smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64 --=20 2.43.0 From nobody Fri Nov 14 15:21:57 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2025 15:49:37.0867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eb96423-b5a4-400e-e827-08de1c82ec84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6072 Received-SPF: permerror client-ip=2a01:111:f403:c001::2; envelope-from=skolothumtho@nvidia.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1762357860756158501 Install an event handler on the vEVENTQ fd to read and propagate host generated vIOMMU events to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 62 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 2 ++ 2 files changed, 64 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 210e7ebf36..e6c81c4786 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -383,6 +383,62 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUSta= te *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static void smmuv3_accel_event_read(void *opaque) +{ + SMMUv3State *s =3D opaque; + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUViommu *vsmmu =3D s_accel->vsmmu; + struct iommu_vevent_arm_smmuv3 *vevent; + struct iommufd_vevent_header *hdr; + ssize_t readsz =3D sizeof(*hdr) + sizeof(*vevent); + uint8_t buf[sizeof(*hdr) + sizeof(*vevent)]; + uint32_t last_seq =3D vsmmu->last_event_seq; + ssize_t bytes; + Evt evt =3D {}; + + bytes =3D read(vsmmu->veventq->veventq_fd, buf, readsz); + if (bytes <=3D 0) { + if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { + return; + } + error_report("vEVENTQ: read failed (%s)", strerror(errno)); + return; + } + + if (bytes < readsz) { + error_report("vEVENTQ: incomplete read (%zd/%zd bytes)", bytes, re= adsz); + return; + } + + hdr =3D (struct iommufd_vevent_header *)buf; + if (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS) { + error_report("vEVENTQ has lost events"); + return; + } + + vevent =3D (struct iommu_vevent_arm_smmuv3 *)(buf + sizeof(*hdr)); + /* Check sequence in hdr for lost events if any */ + if (vsmmu->event_start) { + uint32_t expected =3D (last_seq =3D=3D INT_MAX) ? 0 : last_seq + 1; + + if (hdr->sequence !=3D expected) { + uint32_t delta; + + if (hdr->sequence >=3D last_seq) { + delta =3D hdr->sequence - last_seq; + } else { + /* Handle wraparound from INT_MAX */ + delta =3D (INT_MAX - last_seq) + hdr->sequence + 1; + } + error_report("vEVENTQ: detected lost %u event(s)", delta - 1); + } + } + vsmmu->last_event_seq =3D hdr->sequence; + vsmmu->event_start =3D true; + memcpy(&evt, vevent, sizeof(evt)); + smmuv3_propagate_event(s, &evt); +} + static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) { IOMMUFDVeventq *veventq =3D vsmmu->veventq; @@ -390,6 +446,8 @@ static void smmuv3_accel_free_veventq(SMMUViommu *vsmmu) if (!veventq) { return; } + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); + close(veventq->veventq_fd); iommufd_backend_free_id(vsmmu->iommufd, veventq->veventq_id); g_free(veventq); vsmmu->veventq =3D NULL; @@ -433,6 +491,10 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error = **errp) veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D &vsmmu->viommu; vsmmu->veventq =3D veventq; + + /* Set up event handler for veventq fd */ + fcntl(veventq_fd, F_SETFL, O_NONBLOCK); + qemu_set_fd_handler(veventq_fd, smmuv3_accel_event_read, NULL, s); return true; } =20 diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 740253bc34..6ed5f3b821 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -23,6 +23,8 @@ typedef struct SMMUViommu { IOMMUFDBackend *iommufd; IOMMUFDViommu viommu; IOMMUFDVeventq *veventq; + uint32_t last_event_seq; + bool event_start; uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; --=20 2.43.0