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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1762343214; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=29LUfHiShuavtJENtMDfqPVZdMKOAjQ5KT9Nqx8YzVU=; b=YipcYHaeo9WYTBPl7dXxGvjcaYifYogXoWg4ySbiMkFxIqRYQk44kC95V9AeeeEthFFy5O JuOq/cv9RLjW/NdxOJDWswucUziWZiPifNPZxGp5Fjzew0FX99La+Qar8gHwfrWrtBXRC+ sR9k13Cl8yf3x+Soq7QhdkYzEbyt6RY= X-MC-Unique: JHugRRm5P_qQes0t7qSjWg-1 X-Mimecast-MFC-AGG-ID: JHugRRm5P_qQes0t7qSjWg_1762343209 From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, jonathan.cameron@huawei.com, mchehab+huawei@kernel.org, gengdongjiu1@gmail.com, mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com, peter.maydell@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v3 8/8] target/arm/kvm: Support multiple memory CPERs injection Date: Wed, 5 Nov 2025 21:44:53 +1000 Message-ID: <20251105114453.2164073-9-gshan@redhat.com> In-Reply-To: <20251105114453.2164073-1-gshan@redhat.com> References: <20251105114453.2164073-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In the combination of 64KiB host and 4KiB guest, a problematic host page affects 16x guest pages that can be owned by different threads. It means 16x memory errors can be raised at once due to the parallel accesses to those 16x guest pages on the guest. Unfortunately, QEMU can't deliver them one by one because we just one GHES error block, corresponding one read acknowledgement register. It can eventually cause QEMU crash dump due to the contention on that register, meaning the current memory error can't be delivered before the previous error isn't acknowledged. Imporve push_ghes_memory_errors() to push 16x consecutive memory errors under this situation to avoid the contention on the read acknowledgement register. Signed-off-by: Gavin Shan --- target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5b151eda3c..d7de8262da 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -11,6 +11,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include =20 #include @@ -2432,12 +2433,59 @@ int kvm_arch_get_registers(CPUState *cs, Error **er= rp) static void push_ghes_memory_errors(CPUState *c, AcpiGhesState *ags, uint64_t paddr, Error **errp) { + uint64_t val, start, end, guest_pgsz, host_pgsz; uint64_t addresses[16]; + uint32_t num_of_addresses; + int ret; + + /* + * Sort out the guest page size from TCR_EL1, which can be modified + * by the guest from time to time. So we have to sort it out dynamical= ly. + */ + ret =3D read_sys_reg64(c->kvm_fd, &val, ARM64_SYS_REG(3, 0, 2, 0, 2)); + if (ret) { + error_setg(errp, "Error %" PRId32 " to read TCR_EL1 register", ret= ); + return; + } + + switch (extract64(val, 14, 2)) { + case 0: + guest_pgsz =3D 4 * KiB; + break; + case 1: + guest_pgsz =3D 64 * KiB; + break; + case 2: + guest_pgsz =3D 16 * KiB; + break; + default: + error_setg(errp, "Unknown page size from TCR_EL1 (0x%" PRIx64 ")",= val); + return; + } + + host_pgsz =3D qemu_real_host_page_size(); + start =3D paddr & ~(host_pgsz - 1); + end =3D start + host_pgsz; + num_of_addresses =3D 0; =20 - addresses[0] =3D paddr; + while (start < end) { + /* + * The precise physical address is provided for the affected + * guest page that contains @paddr. Otherwise, the starting + * address of the guest page is provided. + */ + if (paddr >=3D start && paddr < (start + guest_pgsz)) { + addresses[num_of_addresses++] =3D paddr; + } else { + addresses[num_of_addresses++] =3D start; + } + + start +=3D guest_pgsz; + } =20 kvm_cpu_synchronize_state(c); - acpi_ghes_memory_errors(ags, ACPI_HEST_SRC_ID_SYNC, addresses, 1, errp= ); + acpi_ghes_memory_errors(ags, ACPI_HEST_SRC_ID_SYNC, + addresses, num_of_addresses, errp); kvm_inject_arm_sea(c); } =20 --=20 2.51.0