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Tue, 04 Nov 2025 23:18:42 -0800 (PST) From: Jerry Zhang Jian To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, qemu-riscv@nongnu.org, kito.cheng@gmail.com, frank.chang@sifive.com, Jerry Zhang Jian Subject: [PATCH] target/riscv: Add bfloat16 and half-float support to GDB stub Date: Tue, 4 Nov 2025 23:18:30 -0800 Message-ID: <20251105071830.946163-1-jerry.zhangjian@sifive.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=jerry.zhangjian@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1762327186257158500 Content-Type: text/plain; charset="utf-8" Add bfloat16 and ieee_half fields to the RISC-V FPU register unions in the GDB target description XML files. This allows GDB to access FPU registers as BFloat16 or IEEE half-precision floating-point values in addition to the existing single and double precision formats. For 64-bit FPU (riscv-64bit-fpu.xml): - Add bfloat16 field to riscv_double union - Add half (ieee_half) field to riscv_double union For 32-bit FPU (riscv-32bit-fpu.xml): - Create new riscv_single union with bfloat16, half, and float fields - Update all 32 FPU registers to use riscv_single type instead of ieee_single This enables GDB users to inspect and modify FPU registers using different floating-point formats: (gdb) print \.bfloat16 (gdb) print \.half (gdb) print \.float (gdb) print \.double This change corresponds to the GDB-side support for these formats: https://sourceware.org/pipermail/gdb-patches/2025-November/222353.html Signed-off-by: Jerry Zhang Jian --- gdb-xml/riscv-32bit-fpu.xml | 70 ++++++++++++++++++++----------------- gdb-xml/riscv-64bit-fpu.xml | 2 ++ 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml index 24aa087031..f0439c626e 100644 --- a/gdb-xml/riscv-32bit-fpu.xml +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -7,36 +7,42 @@ =20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml index d0f17f9984..7d6a44e145 100644 --- a/gdb-xml/riscv-64bit-fpu.xml +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -9,6 +9,8 @@ =20 + + --=20 2.51.0