From nobody Fri Nov 14 17:01:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315322; cv=none; d=zohomail.com; s=zohoarc; b=MOupB3A5HppYn57ENCfwgGeaVZGJHkdACkoLDfkQ3/XQmqElmP8kCU5gSQUJ2dRQKa1xISiJqaR6mFJw9M2hL2eRTwpeSsj5gFyqyIEaeFXzF15lCtJ7tfoTuxx0gba95nxGSTZm+vM5OQKscbqd7OWrcKqg0g+uFf8l6vfoNho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315322; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mU3vqkPlRUB2dnDi7TnjTT3IGr8DLaBlzCvk47+TA60=; b=oIS1o04yeQGEDjDJ402fZdqJDnIBWi/mvko0T0rPO/B6iU3wI0rffa7wa4ZsuQXEZgFMIY1Xk+9o64eJDhtGB9vk+caTli0TMSB2PDLCx0MjSEwSbzysqSh1b+mASzB9F3/ABxM0xTsVzu/VeH+/X38f9wUtsZT+qBWtO5HpR+A= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315322767705.8729223526959; Tue, 4 Nov 2025 20:02:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgD-0007Xv-4z; Tue, 04 Nov 2025 22:59:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgB-0007XK-KA; Tue, 04 Nov 2025 22:59:27 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgA-0006sZ-50; Tue, 04 Nov 2025 22:59:27 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 07/17] hw/arm/aspeed: Attach UART device to AST1700 model Date: Wed, 5 Nov 2025 11:58:45 +0800 Message-ID: <20251105035859.3709907-8-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315323872154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the UART controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast27x0.c | 2 ++ hw/misc/aspeed_ast1700.c | 26 ++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index c2bea11346..e105ceb027 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -28,8 +28,10 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + hwaddr mapped_base; =20 AspeedLTPIState ltpi; + SerialMM uart; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 11625e165a..7151feb35d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1070,6 +1070,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + qdev_prop_set_uint64(DEVICE(&s->ioexp[i]), "mapped-base", + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; } diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 0ca2b90ff0..1c2d367cdb 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -18,22 +18,39 @@ #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 enum { + ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + hwaddr uart_base; =20 /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* UART */ + uart_base =3D s->mapped_base + + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12]; + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(&s->uart), uart_base, 2); + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDI= AN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -47,6 +64,10 @@ static void aspeed_ast1700_instance_init(Object *obj) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); =20 + /* UART */ + object_initialize_child(obj, "uart[*]", &s->uart, + TYPE_SERIAL_MM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -54,11 +75,16 @@ static void aspeed_ast1700_instance_init(Object *obj) return; } =20 +static const Property aspeed_ast1700_props[] =3D { + DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, = 0), +}; + static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_ast1700_realize; + device_class_set_props(dc, aspeed_ast1700_props); } =20 static const TypeInfo aspeed_ast1700_info =3D { --=20 2.43.0