From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315274; cv=none; d=zohomail.com; s=zohoarc; b=beaNrzLhJxY3YQSG08lglCfBNHJ8j81LSby6l3LKQuLhwCe6Tod/c/tXAiD16sbuVtE4GbWQg8eWLInbt7KwrarTOSHyS5m6p4aYi12Bm51Doc+1LE53uzLMipkb2mfVWxmDl8Gwl79APVoZG7KR0y2bv/1PaqSzFvk+Pt64MFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315274; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=SFowBBQh5bc+pB6op2ogx/Ac4LpLhPwjvsZx7TUDPxs=; b=Q2b+AzbkKx5lME7VmsmQtE6RlMwUhKxO2cvDp5YQiXfXswc+b+TqZhLAx9r+dWkyPxKV0+OgAoBcey4FmjKxNEXUHz0uvSgu2/NiX7qW7m/rr73ULHDf8dvBKTmNT9uMPFNEY8MHpKsPVxxBu6zjIrEe4Pjq8VAyIS8sqeosiZs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315274086348.5092884214224; Tue, 4 Nov 2025 20:01:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUfy-0007Sr-A5; Tue, 04 Nov 2025 22:59:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUfw-0007SY-7M; Tue, 04 Nov 2025 22:59:12 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUfu-0006sZ-Fe; Tue, 04 Nov 2025 22:59:11 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 01/17] hw/arm/aspeed: Add LTPI controller Date: Wed, 5 Nov 2025 11:58:39 +0800 Message-ID: <20251105035859.3709907-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315276711158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM 2.0 specification: https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf LTPI is a protocol and physical interface for tunneling various low-speed signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left) integrates two LTPI controllers, allowing it to connect to up to two extended boards. This commit introduces a simple device model for the ASPEED LTPI controller in QEMU. The model includes basic MMIO read/write operations and sets default register values during reset to emulate a link-up state. Implements register space with read/write callbacks. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ltpi.h | 25 +++++++++ hw/misc/aspeed_ltpi.c | 98 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 124 insertions(+) create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 hw/misc/aspeed_ltpi.c diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h new file mode 100644 index 0000000000..2c31a555dd --- /dev/null +++ b/include/hw/misc/aspeed_ltpi.h @@ -0,0 +1,25 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_LTPI_H +#define ASPEED_LTPI_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI) + +#define ASPEED_LTPI_NR_REGS (0x900 >> 2) + +struct AspeedLTPIState { + SysBusDevice parent; + MemoryRegion mmio; + + uint32_t regs[ASPEED_LTPI_NR_REGS]; +}; + +#endif /* ASPEED_LTPI_H */ diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c new file mode 100644 index 0000000000..fdb71077a4 --- /dev/null +++ b/hw/misc/aspeed_ltpi.c @@ -0,0 +1,98 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ltpi.h" + +#define LTPI_LINK_MNG 0x42 +#define LTPI_PHY_MODE 0x80 + +static uint64_t aspeed_ltpi_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->regs[idx]; +} + +static void aspeed_ltpi_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_ops =3D { + .read =3D aspeed_ltpi_read, + .write =3D aspeed_ltpi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_ltpi_reset(DeviceState *dev) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + memset(s->regs, 0, sizeof(s->regs)); + /* set default values */ + s->regs[LTPI_LINK_MNG] =3D 0x11900007; + s->regs[LTPI_PHY_MODE] =3D 0x2; +} + + +static const VMStateDescription vmstate_aspeed_ltpi =3D { + .name =3D TYPE_ASPEED_LTPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedLTPIState, + ASPEED_LTPI_NR_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_ltpi_ops, s, + TYPE_ASPEED_LTPI, ASPEED_LTPI_NR_REGS); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); +} + +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_ltpi_realize; + dc->vmsd =3D &vmstate_aspeed_ltpi; + device_class_set_legacy_reset(dc, aspeed_ltpi_reset); +} + +static const TypeInfo aspeed_ltpi_info =3D { + .name =3D TYPE_ASPEED_LTPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedLTPIState), + .class_init =3D aspeed_ltpi_class_init, +}; + +static void aspeed_ltpi_register_types(void) +{ + type_register_static(&aspeed_ltpi_info); +} + +type_init(aspeed_ltpi_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..45b16e7797 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', + 'aspeed_ltpi.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315285179658.9365792164987; Tue, 4 Nov 2025 20:01:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUfz-0007To-Ti; Tue, 04 Nov 2025 22:59:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUfy-0007Sv-L0; Tue, 04 Nov 2025 22:59:14 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUfx-0006sZ-1l; Tue, 04 Nov 2025 22:59:14 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 02/17] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Date: Wed, 5 Nov 2025 11:58:40 +0800 Message-ID: <20251105035859.3709907-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315287763154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the LTPI controller device (representing the AST1700 I/O expander) to the AST27X0 SoC model. This patch sets up the memory mapping and device registration according to the AST2700 SoC design, where the LTPI controller is exposed at fixed MMIO regions. This change only handles device instantiation and integration, without implementing the controller's internal logic. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 5 +++++ hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4b8e599f1a..bae60d85ea 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -42,6 +42,7 @@ #include "hw/fsi/aspeed_apb2opb.h" #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -53,6 +54,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { DeviceState parent; @@ -110,6 +112,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -275,6 +278,8 @@ enum { ASPEED_GIC_REDIST, ASPEED_DEV_IPC0, ASPEED_DEV_IPC1, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c484bcd4e2..c0d8639bde 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -86,6 +86,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_UART10] =3D 0x14C33900, [ASPEED_DEV_UART11] =3D 0x14C33A00, [ASPEED_DEV_UART12] =3D 0x14C33B00, + [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, + [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, @@ -543,6 +545,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort= ); } =20 + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + object_initialize_child(obj, "ltpi-ctrl[*]", + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); + } object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "ltpi", &s->ltpi, @@ -688,6 +694,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) g_autofree char *name =3D NULL; qemu_irq irq; int uart; + AspeedLTPIState *ltpi_ctrl; + hwaddr ltpi_base; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -1021,6 +1029,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) return; } =20 + /* LTPI controller */ + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[i]); + ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i]; + + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); + } aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315224832717.7909994787445; Tue, 4 Nov 2025 20:00:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUg5-0007Uo-RT; Tue, 04 Nov 2025 22:59:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg1-0007Tx-Lb; Tue, 04 Nov 2025 22:59:17 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUfz-0006sZ-Ub; Tue, 04 Nov 2025 22:59:17 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 03/17] hw/arm/aspeed: Add AST1700 LTPI expander device model Date: Wed, 5 Nov 2025 11:58:41 +0800 Message-ID: <20251105035859.3709907-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315227437154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Introduce a minimal QEMU device model for the ASPEED AST1700, an MCU-less I/O expander used in the LTPI topology defined by the DC-SCM 2.0 specification (see figure 2): https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf This initial implementation includes: * Definition of aspeed.ast1700 as a SysBusDevice * Setup of a basic memory region to reserve I/O space for future peripheral modeling This stub establishes the foundation for LTPI-related device emulation, without implementing any functional peripherals at this stage. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 32 ++++++++++++++++++ hw/misc/aspeed_ast1700.c | 57 ++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 90 insertions(+) create mode 100644 include/hw/misc/aspeed_ast1700.h create mode 100644 hw/misc/aspeed_ast1700.c diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h new file mode 100644 index 0000000000..b7c666eef2 --- /dev/null +++ b/include/hw/misc/aspeed_ast1700.h @@ -0,0 +1,32 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_AST1700_H +#define ASPEED_AST1700_H + +#include "hw/sysbus.h" +#include "hw/misc/aspeed_scu.h" +#include "hw/adc/aspeed_adc.h" +#include "hw/gpio/aspeed_gpio.h" +#include "hw/i2c/aspeed_i2c.h" +#include "hw/misc/aspeed_ltpi.h" +#include "hw/ssi/aspeed_smc.h" +#include "hw/watchdog/wdt_aspeed.h" +#include "hw/char/serial-mm.h" +#include "hw/misc/unimp.h" + +#define TYPE_ASPEED_AST1700 "aspeed.ast1700" + +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) + +struct AspeedAST1700SoCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; +}; + +#endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c new file mode 100644 index 0000000000..bb05e392f4 --- /dev/null +++ b/hw/misc/aspeed_ast1700.c @@ -0,0 +1,57 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/qdev-core.h" +#include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ast1700.h" + +#define AST2700_SOC_LTPI_SIZE 0x01000000 +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) +{ + AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + /* Occupy memory space for all controllers in AST1700 */ + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, + AST2700_SOC_LTPI_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + +} + +static void aspeed_ast1700_instance_init(Object *obj) +{ + return; +} + +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_ast1700_realize; +} + +static const TypeInfo aspeed_ast1700_info =3D { + .name =3D TYPE_ASPEED_AST1700, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedAST1700SoCState), + .class_init =3D aspeed_ast1700_class_init, + .instance_init =3D aspeed_ast1700_instance_init, +}; + + +static void aspeed_ast1700_register_types(void) +{ + type_register_static(&aspeed_ast1700_info); +} + +type_init(aspeed_ast1700_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 45b16e7797..9477e63cdf 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -133,6 +133,7 @@ system_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: file= s('pvpanic-pci.c')) system_ss.add(when: 'CONFIG_PVPANIC_MMIO', if_true: files('pvpanic-mmio.c'= )) system_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_ast1700.c', 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315209762171.1334910684409; Tue, 4 Nov 2025 20:00:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUg7-0007Vd-7m; Tue, 04 Nov 2025 22:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg4-0007UV-Hl; Tue, 04 Nov 2025 22:59:20 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg2-0006sZ-Sk; Tue, 04 Nov 2025 22:59:20 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 04/17] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Date: Wed, 5 Nov 2025 11:58:42 +0800 Message-ID: <20251105035859.3709907-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315213431154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the AST1700 device as a child of the AST27X0 model to reflect its role in DC-SCM 2.0 LTPI-based architectures. This patch wires the AST1700 device into the platform without introducing functional peripherals. This forms the base for LTPI expander emulation in QEMU using AST27X0 as the host controller. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 9 +++++++-- include/hw/misc/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast27x0.c | 30 ++++++++++++++++++++++-------- hw/misc/aspeed_ast1700.c | 6 ++++++ 4 files changed, 36 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index bae60d85ea..00cd8df038 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -43,6 +43,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/misc/aspeed_ast1700.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -109,10 +110,10 @@ struct AspeedSoCState { UnimplementedDeviceState espi; UnimplementedDeviceState udc; UnimplementedDeviceState sgpiom; - UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -174,6 +175,7 @@ struct AspeedSoCClass { int macs_num; int uarts_num; int uarts_base; + int ioexp_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -186,7 +188,8 @@ enum { ASPEED_DEV_IOMEM, ASPEED_DEV_IOMEM0, ASPEED_DEV_IOMEM1, - ASPEED_DEV_LTPI, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, ASPEED_DEV_UART0, ASPEED_DEV_UART1, ASPEED_DEV_UART2, @@ -280,6 +283,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index b7c666eef2..624ef61eda 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -20,6 +20,7 @@ #include "hw/misc/unimp.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" +#define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700" =20 OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c0d8639bde..054864467d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -26,7 +26,6 @@ #define AST2700_SOC_IO_SIZE 0x00FE0000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 #define AST2700_SOC_DPMCU_SIZE 0x00040000 -#define AST2700_SOC_LTPI_SIZE 0x01000000 =20 static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_VBOOTROM] =3D 0x00000000, @@ -89,11 +88,14 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, + [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, + [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, - [ASPEED_DEV_LTPI] =3D 0x300000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; =20 @@ -549,10 +551,15 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl[*]", &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } + + for (i =3D 0; i < sc->ioexp_num; i++) { + /* AST1700 IOEXP */ + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], + TYPE_ASPEED_AST1700_AST2700); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); - object_initialize_child(obj, "ltpi", &s->ltpi, - TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem0", &s->iomem0, @@ -1039,14 +1046,20 @@ static void aspeed_soc_ast2700_realize(DeviceState = *dev, Error **errp) } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); } + + /* IO Expander */ + for (i =3D 0; i < sc->ioexp_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), - "aspeed.ltpi", - sc->memmap[ASPEED_DEV_LTPI], - AST2700_SOC_LTPI_SIZE); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], @@ -1112,6 +1125,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; + sc->ioexp_num =3D 2; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index bb05e392f4..3125bec795 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -48,10 +48,16 @@ static const TypeInfo aspeed_ast1700_info =3D { .instance_init =3D aspeed_ast1700_instance_init, }; =20 +static const TypeInfo aspeed_ast1700_ast2700_info =3D { + .name =3D TYPE_ASPEED_AST1700_AST2700, + .parent =3D TYPE_ASPEED_AST1700, +}; + =20 static void aspeed_ast1700_register_types(void) { type_register_static(&aspeed_ast1700_info); + type_register_static(&aspeed_ast1700_ast2700_info); } =20 type_init(aspeed_ast1700_register_types); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315210; cv=none; d=zohomail.com; s=zohoarc; b=gJFniO2sVi4j72etHjxwk2Ywr5vU1Y/pSTkFBwJh+vUehli4I42KxpJnXEmkdc9nV/R2fSOm218zOoUXdtKbM2ancmebngpCvLwm5id7vW7cglmwX+RMEtu4TnxwJt7VH7S25CeIhSqKAlYdRNT5L6EJmOR1z80XzqaEWRziX9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315210; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 04 Nov 2025 22:59:22 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 05/17] hw/arm/aspeed: Integrate interrupt controller for AST1700 Date: Wed, 5 Nov 2025 11:58:43 +0800 Message-ID: <20251105035859.3709907-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315213988158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling the propagation of AST1700-originated interrupts to the host SoC. This patch does not implement interrupt sources in AST1700 itself, only the wiring into AST27X0. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 +- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 36 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 99 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 00cd8df038..66a6a073f6 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -143,7 +143,7 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[4]; GICv3State gic; MemoryRegion dram_empty; }; diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 054864467d..11625e165a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -505,6 +505,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intcioexp0", &a->intc[2], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intcioexp1", &a->intc[3], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -701,6 +705,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) g_autofree char *name =3D NULL; qemu_irq irq; int uart; + int j; AspeedLTPIState *ltpi_ctrl; hwaddr ltpi_base; =20 @@ -746,6 +751,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[2]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[2]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[3]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[3]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@ -1054,6 +1075,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + + icio =3D ASPEED_INTC_GET_CLASS(&a->intc[2 + i]); + /* INTC2/3 internal: orgate[i] -> input[i] */ + for (j =3D 0; j < icio->num_inpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intc[2 + i]), j); + qdev_connect_gpio_out(DEVICE(&a->intc[2 + i].orgates[j]), 0, + irq); + } + + /* INTC2/3 output[i] -> INTC0.orgate[0].input[i] */ + for (j =3D 0; j < icio->num_outpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j); + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j, + irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315210; cv=none; d=zohomail.com; s=zohoarc; b=S2Rjg5ZiJE+IApAV+upbNZta6TYfyrJ6r2J9MBqkLFwlT32wFpFV5t9uBFTNw8zJvaz4ra/k0YWD2E2Oc22mAJxzR6CKU5Hsv+ET1smAxUEvUWRztGKFmsiDTu79GiwUxJ+VJGANYGAQRBHemChu2C3mffK7s3naTx0gZc66kb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tue, 04 Nov 2025 22:59:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg9-0007WG-Au; Tue, 04 Nov 2025 22:59:25 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUg7-0006sZ-R7; Tue, 04 Nov 2025 22:59:24 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 06/17] hw/arm/aspeed: Attach LTPI controller to AST1700 model Date: Wed, 5 Nov 2025 11:58:44 +0800 Message-ID: <20251105035859.3709907-7-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315213907158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the LTPI controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_ast1700.h | 2 ++ hw/misc/aspeed_ast1700.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 624ef61eda..c2bea11346 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -28,6 +28,8 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + + AspeedLTPIState ltpi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 3125bec795..0ca2b90ff0 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -16,6 +16,14 @@ #include "hw/misc/aspeed_ast1700.h" =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 + +enum { + ASPEED_AST1700_DEV_LTPI_CTRL, +}; + +static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, +}; static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); @@ -26,10 +34,23 @@ static void aspeed_ast1700_realize(DeviceState *dev, Er= ror **errp) AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* LTPI controller */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); } =20 static void aspeed_ast1700_instance_init(Object *obj) { + AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); + + /* LTPI controller */ + object_initialize_child(obj, "ltpi-ctrl", + &s->ltpi, TYPE_ASPEED_LTPI); + return; } =20 --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315322; 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Wed, 5 Nov 2025 11:59:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 07/17] hw/arm/aspeed: Attach UART device to AST1700 model Date: Wed, 5 Nov 2025 11:58:45 +0800 Message-ID: <20251105035859.3709907-8-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315323872154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the UART controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast27x0.c | 2 ++ hw/misc/aspeed_ast1700.c | 26 ++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index c2bea11346..e105ceb027 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -28,8 +28,10 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + hwaddr mapped_base; =20 AspeedLTPIState ltpi; + SerialMM uart; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 11625e165a..7151feb35d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1070,6 +1070,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + qdev_prop_set_uint64(DEVICE(&s->ioexp[i]), "mapped-base", + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; } diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 0ca2b90ff0..1c2d367cdb 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -18,22 +18,39 @@ #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 enum { + ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + hwaddr uart_base; =20 /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* UART */ + uart_base =3D s->mapped_base + + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12]; + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(&s->uart), uart_base, 2); + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDI= AN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -47,6 +64,10 @@ static void aspeed_ast1700_instance_init(Object *obj) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); =20 + /* UART */ + object_initialize_child(obj, "uart[*]", &s->uart, + TYPE_SERIAL_MM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -54,11 +75,16 @@ static void aspeed_ast1700_instance_init(Object *obj) return; } =20 +static const Property aspeed_ast1700_props[] =3D { + DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, = 0), +}; + static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_ast1700_realize; + device_class_set_props(dc, aspeed_ast1700_props); } =20 static const TypeInfo aspeed_ast1700_info =3D { --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315209; cv=none; d=zohomail.com; s=zohoarc; b=gc5oBBlVfPDKfD7JA4SKXJ1EAyGZ/4hRbjIfMadB4OJNwySfsrYABMvBWJ4KTnlN2PE5Ig/yP/wJ2CnS3ARtDxosqmMQgE5M4RUS6hAnvX9DCnv00qYZYD5flbb3zppSgNyyVm4zzjHvD/DCewDrZDymOTdCa4ebNOin/PfSdrc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315209; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 04 Nov 2025 22:59:29 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 08/17] hw/arm/aspeed: Attach SRAM device to AST1700 model Date: Wed, 5 Nov 2025 11:58:46 +0800 Message-ID: <20251105035859.3709907-9-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315213388154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Map the SRAM device to AST1700 model Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/misc/aspeed_ast1700.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index e105ceb027..391c8687f5 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -32,6 +32,7 @@ struct AspeedAST1700SoCState { =20 AspeedLTPIState ltpi; SerialMM uart; + MemoryRegion sram; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 1c2d367cdb..6f7ff625b5 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -15,14 +15,18 @@ #include "migration/vmstate.h" #include "hw/misc/aspeed_ast1700.h" =20 +#define AST1700_BOARD1_MEM_ADDR 0x30000000 #define AST2700_SOC_LTPI_SIZE 0x01000000 +#define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; @@ -31,12 +35,33 @@ static void aspeed_ast1700_realize(DeviceState *dev, Er= ror **errp) AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); hwaddr uart_base; + Error *err =3D NULL; + int board_idx; + char sram_name[32]; + + if (s->mapped_base =3D=3D AST1700_BOARD1_MEM_ADDR) { + board_idx =3D 0; + } else { + board_idx =3D 1; + } =20 /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* SRAM */ + snprintf(sram_name, sizeof(sram_name), "aspeed.ioexp-sram.%d", board_i= dx); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, + AST1700_SOC_SRAM_SIZE, &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DE= V_SRAM], + &s->sram); + /* UART */ uart_base =3D s->mapped_base + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12]; --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315403722708.5829471550613; Tue, 4 Nov 2025 20:03:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgI-0007a8-6j; Tue, 04 Nov 2025 22:59:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgG-0007ZV-Qp; Tue, 04 Nov 2025 22:59:32 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgF-0006sZ-Da; Tue, 04 Nov 2025 22:59:32 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 09/17] hw/arm/aspeed: Attach SPI device to AST1700 model Date: Wed, 5 Nov 2025 11:58:47 +0800 Message-ID: <20251105035859.3709907-10-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315406456154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the SPI device to AST1700 model. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/misc/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 391c8687f5..e55deea67a 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -33,6 +33,7 @@ struct AspeedAST1700SoCState { AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; + AspeedSMCState spi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 6f7ff625b5..ba44e484e8 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -20,15 +20,19 @@ #define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_SPI0_MEM, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { @@ -76,6 +80,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); =20 + /* SPI */ + object_property_set_link(OBJECT(&s->spi), "dram", + OBJECT(&s->iomem), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0)= ); + + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -88,11 +106,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) static void aspeed_ast1700_instance_init(Object *obj) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); + char socname[8]; + char typename[64]; + + if (sscanf(object_get_typename(obj), "aspeed.ast1700-%7s", socname) != =3D 1) { + g_assert_not_reached(); + } =20 /* UART */ object_initialize_child(obj, "uart[*]", &s->uart, TYPE_SERIAL_MM); =20 + /* SPI */ + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0, socname); + object_initialize_child(obj, "ioexp-spi[*]", &s->spi, + typename); /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315209; cv=none; d=zohomail.com; s=zohoarc; b=ht69rYYU6M6xt7CIlSNH+PnwB5JehKgRuE+prH/4Yus2l4BjyrQyLNj4UBSFdBO3HhzN9B6i5T9y/u6PRpGL/I4V4Q61h99IzLXq9hSuA1NmOEVyp+Ac3uM6ujmWsuO1kwrKdcEjrPKphB38O/pzt4tIncF6W/SCO5tJjcKI280= ARC-Message-Signature: i=1; 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Tue, 04 Nov 2025 22:59:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgK-0007bG-OS; Tue, 04 Nov 2025 22:59:36 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgJ-0008AS-C9; Tue, 04 Nov 2025 22:59:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 10/17] hw/arm/aspeed: Attach ADC device to AST1700 model Date: Wed, 5 Nov 2025 11:58:48 +0800 Message-ID: <20251105035859.3709907-11-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315212794158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the ADC device to AST1700 model. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast27x0.c | 4 ++++ hw/misc/aspeed_ast1700.c | 15 +++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index e55deea67a..dc9aa08c24 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -34,6 +34,7 @@ struct AspeedAST1700SoCState { SerialMM uart; MemoryRegion sram; AspeedSMCState spi; + AspeedADCState adc; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 7151feb35d..75bb18b9c1 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1092,6 +1092,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[2 + i]), j, irq); } + + /* ADC */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index ba44e484e8..d06603a048 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -22,6 +22,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, + ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -30,6 +31,7 @@ enum { static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, + [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -94,6 +96,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); =20 + /* ADC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -121,6 +131,11 @@ static void aspeed_ast1700_instance_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", 0, socname); object_initialize_child(obj, "ioexp-spi[*]", &s->spi, typename); + + /* ADC */ + snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); + object_initialize_child(obj, "ioexp-adc[*]", &s->adc, + typename); /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315394771558.7359705645694; Tue, 4 Nov 2025 20:03:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgY-0007hE-Rn; Tue, 04 Nov 2025 22:59:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgM-0007bj-Ua; Tue, 04 Nov 2025 22:59:39 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgL-0008AS-JE; Tue, 04 Nov 2025 22:59:38 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 11/17] hw/arm/aspeed: Attach SCU device to AST1700 model Date: Wed, 5 Nov 2025 11:58:49 +0800 Message-ID: <20251105035859.3709907-12-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315395227158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the SCU device to AST1700 model. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast27x0.c | 2 ++ hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index dc9aa08c24..c54600281e 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -29,12 +29,14 @@ struct AspeedAST1700SoCState { =20 MemoryRegion iomem; hwaddr mapped_base; + uint32_t silicon_rev; =20 AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; AspeedSMCState spi; AspeedADCState adc; + AspeedSCUState scu; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 75bb18b9c1..312a1a7eea 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -560,6 +560,8 @@ static void aspeed_soc_ast2700_init(Object *obj) /* AST1700 IOEXP */ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], TYPE_ASPEED_AST1700_AST2700); + qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev", + sc->silicon_rev); } =20 object_initialize_child(obj, "dpmcu", &s->dpmcu, diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index d06603a048..9b203afb9c 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -23,6 +23,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, + ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -32,6 +33,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, + [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -104,6 +106,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); =20 + /* SCU */ + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", + s->silicon_rev); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -136,6 +148,10 @@ static void aspeed_ast1700_instance_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "ioexp-adc[*]", &s->adc, typename); + + /* SCU */ + object_initialize_child(obj, "ioexp-scu[*]", &s->scu, + TYPE_ASPEED_2700_SCU); /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -145,6 +161,7 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT64("mapped-base", AspeedAST1700SoCState, mapped_base, = 0), + DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, = 0), }; =20 static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762315400; cv=none; d=zohomail.com; s=zohoarc; b=IfTw6Ykt90ZVz/CE/d877ShyBTrm0eeUzzMoyRNbOkUAoz3NB4Kl78A2S75IaAsqa8j0K0zd6Heeb5tf7B4oPu43bfLURd3pX/dcsaJHLkPw4Cv6/FYE3CwQ2SiR/wQHjxw6Y3fkZvFGqaX+YClmj2PlQLgj1i0rjCNzBvohRL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762315400; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 04 Nov 2025 22:59:41 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 12/17] hw/arm/aspeed: Attach GPIO device to AST1700 model Date: Wed, 5 Nov 2025 11:58:50 +0800 Message-ID: <20251105035859.3709907-13-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315405295158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the GPIO controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast27x0.c | 4 ++++ hw/misc/aspeed_ast1700.c | 14 ++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index c54600281e..37bbb7932f 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -37,6 +37,7 @@ struct AspeedAST1700SoCState { AspeedSMCState spi; AspeedADCState adc; AspeedSCUState scu; + AspeedGPIOState gpio; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 312a1a7eea..fb03fbebfd 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1098,6 +1098,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) /* ADC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); + + /* GPIO */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 9b203afb9c..2b2934155b 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -24,6 +24,7 @@ enum { ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, + ASPEED_AST1700_DEV_GPIO, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -34,6 +35,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, + [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -116,6 +118,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); =20 + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -152,6 +162,10 @@ static void aspeed_ast1700_instance_init(Object *obj) /* SCU */ object_initialize_child(obj, "ioexp-scu[*]", &s->scu, TYPE_ASPEED_2700_SCU); + + /* GPIO */ + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); + object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, typename); /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315355274990.8079403001226; Tue, 4 Nov 2025 20:02:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgo-00082y-CX; Tue, 04 Nov 2025 23:00:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgm-00082h-GR; Tue, 04 Nov 2025 23:00:04 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgk-0008AS-Nv; Tue, 04 Nov 2025 23:00:04 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 13/17] hw/arm/aspeed: Attach I2C device to AST1700 model Date: Wed, 5 Nov 2025 11:58:51 +0800 Message-ID: <20251105035859.3709907-14-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315359033158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the I2C controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 ++ include/hw/misc/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast27x0.c | 39 ++++++++++++++++++++++++++++++-- hw/misc/aspeed_ast1700.c | 17 ++++++++++++++ 4 files changed, 57 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 66a6a073f6..464ef2d755 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -283,6 +283,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 37bbb7932f..4aefb7ea35 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -38,6 +38,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedI2CState i2c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index fb03fbebfd..a5d98f541b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -199,6 +199,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 128 */ @@ -259,6 +261,17 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -275,9 +288,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {195, 1, 3, ast2700_gic131_gic195_intcmap}, {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, - {198, 1, 6, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, {199, 1, 7, NULL}, - {200, 1, 8, NULL}, + {200, 3, 0, ast2700_gic200_intcmap}, {201, 1, 9, NULL}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, @@ -708,6 +721,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) qemu_irq irq; int uart; int j; + AspeedI2CClass *i2c_ctl; AspeedLTPIState *ltpi_ctrl; hwaddr ltpi_base; =20 @@ -1102,6 +1116,27 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) /* GPIO */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); + + /* I2C */ + i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c); + for (j =3D 0; j < i2c_ctl->num_busses; j++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 = to bit + * 15, and the OR gate output pin is connected to the input pi= n of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Th= en, + * the output pin is connected to the INTC (CPU Die) input pin= , and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C += i, + j); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]), + 0, irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 2b2934155b..6c7483c88c 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -25,6 +25,7 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -36,6 +37,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -126,6 +128,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); =20 + /* I2C */ + object_property_set_link(OBJECT(&s->i2c), "dram", + OBJECT(&s->iomem), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -166,6 +178,11 @@ static void aspeed_ast1700_instance_init(Object *obj) /* GPIO */ snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, typename); + + /* I2C */ + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); + object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, + typename); /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315256411594.3606189385225; Tue, 4 Nov 2025 20:00:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgv-0008O4-O5; Tue, 04 Nov 2025 23:00:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgs-0008HA-8j; Tue, 04 Nov 2025 23:00:10 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgq-0000YI-LP; Tue, 04 Nov 2025 23:00:10 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 14/17] hw/arm/aspeed: Attach WDT device to AST1700 model Date: Wed, 5 Nov 2025 11:58:52 +0800 Message-ID: <20251105035859.3709907-15-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315259152154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the WDT device to AST1700 model. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 3 +++ hw/misc/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 4aefb7ea35..f89de44539 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -19,6 +19,8 @@ #include "hw/char/serial-mm.h" #include "hw/misc/unimp.h" =20 +#define AST1700_WDT_NUM 9 + #define TYPE_ASPEED_AST1700 "aspeed.ast1700" #define TYPE_ASPEED_AST1700_AST2700 "aspeed.ast1700-ast2700" =20 @@ -39,6 +41,7 @@ struct AspeedAST1700SoCState { AspeedSCUState scu; AspeedGPIOState gpio; AspeedI2CState i2c; + AspeedWDTState wdt[AST1700_WDT_NUM]; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 6c7483c88c..c2dc834b4f 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -28,6 +28,7 @@ enum { ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_WDT, ASPEED_AST1700_DEV_SPI0_MEM, }; =20 @@ -40,10 +41,13 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; + static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { + int i; AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); hwaddr uart_base; @@ -145,10 +149,27 @@ static void aspeed_ast1700_realize(DeviceState *dev, = Error **errp) memory_region_add_subregion(&s->iomem, aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); + + /* WDT */ + for (i =3D 0; i < AST1700_WDT_NUM; i++) { + AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); + hwaddr wdt_offset =3D aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_= WDT] + + i * awc->iosize; + + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + wdt_offset, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); + } } =20 static void aspeed_ast1700_instance_init(Object *obj) { + int i; AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); char socname[8]; char typename[64]; @@ -187,6 +208,13 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* WDT */ + for (i =3D 0; i < AST1700_WDT_NUM; i++) { + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); + object_initialize_child(obj, "ioexp-wdt[*]", + &s->wdt[i], typename); + } + return; } =20 --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315402503589.054710574416; Tue, 4 Nov 2025 20:03:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgx-0008SS-Vs; Tue, 04 Nov 2025 23:00:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgu-0008O3-UG; Tue, 04 Nov 2025 23:00:13 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgt-0000YI-36; Tue, 04 Nov 2025 23:00:12 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 15/17] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Date: Wed, 5 Nov 2025 11:58:53 +0800 Message-ID: <20251105035859.3709907-16-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315404556154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 exposes more I3C buses than the current dummy I3C model provides. When Linux probes the I3C devices on AST1700 this mismatch can trigger a kernel panic. Model the I3C block as an unimplemented device to make the missing functionality explicit and avoid unexpected side effects. This wires up the I3C interrupt lines for the IO expanders and adds the corresponding device entries for the AST1700 model. No functional I3C emulation is provided yet; this only prevents crashes and documents the missing piece. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 2 ++ include/hw/misc/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast27x0.c | 19 +++++++++++++++++-- hw/misc/aspeed_ast1700.c | 17 +++++++++++++++++ 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 464ef2d755..c58c861841 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -287,6 +287,8 @@ enum { ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, + ASPEED_DEV_IOEXP0_I3C, + ASPEED_DEV_IOEXP1_I3C, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index f89de44539..4048d31154 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -42,6 +42,8 @@ struct AspeedAST1700SoCState { AspeedGPIOState gpio; AspeedI2CState i2c; AspeedWDTState wdt[AST1700_WDT_NUM]; + + UnimplementedDeviceState i3c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index a5d98f541b..f8dd4f6a3a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -200,7 +200,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP0_I3C] =3D 199, [ASPEED_DEV_IOEXP1_I2C] =3D 200, + [ASPEED_DEV_IOEXP1_I3C] =3D 201, }; =20 /* GICINT 128 */ @@ -267,11 +269,24 @@ static const int ast2700_gic198_intcmap[] =3D { [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I3C] =3D 0, /* 0 - 15 */ +}; + /* Secondary AST1700 Interrupts */ /* A1: GINTC 200 */ static const int ast2700_gic200_intcmap[] =3D { [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ }; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I3C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -289,9 +304,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, {198, 2, 0, ast2700_gic198_intcmap}, - {199, 1, 7, NULL}, + {199, 2, 1, ast2700_gic199_intcmap}, {200, 3, 0, ast2700_gic200_intcmap}, - {201, 1, 9, NULL}, + {201, 3, 1, ast2700_gic201_intcmap}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, {130, 0, 3, ast2700_gic130_gic194_intcmap}, diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index c2dc834b4f..37b2946fc0 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -18,6 +18,7 @@ #define AST1700_BOARD1_MEM_ADDR 0x30000000 #define AST2700_SOC_LTPI_SIZE 0x01000000 #define AST1700_SOC_SRAM_SIZE 0x00040000 +#define AST1700_SOC_I3C_SIZE 0x00010000 =20 enum { ASPEED_AST1700_DEV_SPI0, @@ -26,6 +27,7 @@ enum { ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, ASPEED_AST1700_DEV_I2C, + ASPEED_AST1700_DEV_I3C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_WDT, @@ -39,6 +41,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, + [ASPEED_AST1700_DEV_I3C] =3D 0x00C20000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, @@ -142,6 +145,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); =20 + /* I3C */ + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c"); + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0), + -1000); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -204,6 +216,11 @@ static void aspeed_ast1700_instance_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, typename); + + /* I3C */ + object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c, + TYPE_UNIMPLEMENTED_DEVICE); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762315239321870.5689202438992; Tue, 4 Nov 2025 20:00:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGUgz-0008T1-33; Tue, 04 Nov 2025 23:00:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgx-0008S5-Bu; Tue, 04 Nov 2025 23:00:15 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGUgv-0000YI-RS; Tue, 04 Nov 2025 23:00:15 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 5 Nov 2025 11:59:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 16/17] hw/arm/aspeed: Model AST1700 SGPIOM block as unimplemented device Date: Wed, 5 Nov 2025 11:58:54 +0800 Message-ID: <20251105035859.3709907-17-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315241295154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 includes an SGPIOM block, but QEMU has no functional model yet. Expose it as an unimplemented device so the address space is reserved and the missing functionality is explicit to users/guests. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 4048d31154..8ada3a7775 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -44,6 +44,7 @@ struct AspeedAST1700SoCState { AspeedWDTState wdt[AST1700_WDT_NUM]; =20 UnimplementedDeviceState i3c; + UnimplementedDeviceState sgpiom; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 37b2946fc0..66a5f21d27 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -19,6 +19,7 @@ #define AST2700_SOC_LTPI_SIZE 0x01000000 #define AST1700_SOC_SRAM_SIZE 0x00040000 #define AST1700_SOC_I3C_SIZE 0x00010000 +#define AST1700_SOC_SGPIOM_SIZE 0x00002000 =20 enum { ASPEED_AST1700_DEV_SPI0, @@ -26,6 +27,7 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_SGPIOM, ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_I3C, ASPEED_AST1700_DEV_UART12, @@ -40,6 +42,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_SGPIOM] =3D 0x00C0C000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_I3C] =3D 0x00C20000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, @@ -162,6 +165,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); =20 + /* SGPIOM */ + qdev_prop_set_string(DEVICE(&s->sgpiom), "name", "ioexp-sgpiom"); + qdev_prop_set_uint64(DEVICE(&s->sgpiom), "size", AST1700_SOC_SGPIOM_SI= ZE); + sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM= ], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom),= 0), + -1000); + /* WDT */ for (i =3D 0; i < AST1700_WDT_NUM; i++) { AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@ -225,6 +237,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* SGPIOM */ + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom, + TYPE_UNIMPLEMENTED_DEVICE); + /* WDT */ for (i =3D 0; i < AST1700_WDT_NUM; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); --=20 2.43.0 From nobody Fri Nov 14 15:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 5 Nov 2025 11:59:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 5 Nov 2025 11:59:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 17/17] hw/arm/aspeed: Model AST1700 PWM block as unimplemented device Date: Wed, 5 Nov 2025 11:58:55 +0800 Message-ID: <20251105035859.3709907-18-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251105035859.3709907-1-kane_chen@aspeedtech.com> References: <20251105035859.3709907-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762315296774158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 includes an PWM block, but QEMU has no functional model for aspeed product yet. Expose it as an unimplemented device so the address space is reserved and the missing functionality is explicit to users/guests. Signed-off-by: Kane-Chen-AS --- include/hw/misc/aspeed_ast1700.h | 1 + hw/misc/aspeed_ast1700.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/misc/aspeed_ast1700.h b/include/hw/misc/aspeed_ast1= 700.h index 8ada3a7775..9d432a7db0 100644 --- a/include/hw/misc/aspeed_ast1700.h +++ b/include/hw/misc/aspeed_ast1700.h @@ -45,6 +45,7 @@ struct AspeedAST1700SoCState { =20 UnimplementedDeviceState i3c; UnimplementedDeviceState sgpiom; + UnimplementedDeviceState pwm; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/misc/aspeed_ast1700.c b/hw/misc/aspeed_ast1700.c index 66a5f21d27..3d9a920a7a 100644 --- a/hw/misc/aspeed_ast1700.c +++ b/hw/misc/aspeed_ast1700.c @@ -20,9 +20,11 @@ #define AST1700_SOC_SRAM_SIZE 0x00040000 #define AST1700_SOC_I3C_SIZE 0x00010000 #define AST1700_SOC_SGPIOM_SIZE 0x00002000 +#define AST1700_SOC_PWM_SIZE 0x00000200 =20 enum { ASPEED_AST1700_DEV_SPI0, + ASPEED_AST1700_DEV_PWM, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, @@ -38,6 +40,7 @@ enum { =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, + [ASPEED_AST1700_DEV_PWM] =3D 0x000C0000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, @@ -174,6 +177,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom),= 0), -1000); =20 + /* PWM */ + qdev_prop_set_string(DEVICE(&s->pwm), "name", "ioexp-pwm"); + qdev_prop_set_uint64(DEVICE(&s->pwm), "size", AST1700_SOC_PWM_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0), + -1000); + /* WDT */ for (i =3D 0; i < AST1700_WDT_NUM; i++) { AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@ -241,6 +253,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom, TYPE_UNIMPLEMENTED_DEVICE); =20 + /* PWM */ + object_initialize_child(obj, "ioexp-pwm", &s->pwm, + TYPE_UNIMPLEMENTED_DEVICE); + /* WDT */ for (i =3D 0; i < AST1700_WDT_NUM; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); --=20 2.43.0