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Tue, 04 Nov 2025 12:51:04 -0800 (PST) From: Gabriel Brookman Date: Tue, 04 Nov 2025 15:50:00 -0500 Subject: [PATCH] target/arm: add support for FEAT_MTE_TAGGED_FAR MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251104-feat-mte-tagged-far-v1-1-cdfd7db40397@gmail.com> X-B4-Tracking: v=1; b=H4sIAPdmCmkC/x3MQQqAIBBA0avIrBtQK5CuEi2GHG0WWahEEN09a fkW/z9QOAsXmNQDmS8pcqQG0ylYN0qRUXwzWG1HY/SAganiXhkrxcgeA2Vcne+1JecceWjlmTn I/V/n5X0/koOOuGUAAAA= X-Change-ID: 20251104-feat-mte-tagged-far-c8d302a888ad To: qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org, Gabriel Brookman X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762289463; l=3805; i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id; bh=AmAGdnlPNeY/wfLgYtaHqGABhjeGNyiiTYow65UsP1E=; b=dO9yd/A9m+bfodyCw8TDAnw2vCJ4XrQM7sM+qr+6wYfycD+bkLtM7tuZYw6Ns3MFz7yF04NKk tX9c1ENtssTD+2Dynrw3kYpAX9iwtJiZqrgAm/GB7vPlMdoanYYOXWx X-Developer-Key: i=brookmangabriel@gmail.com; a=ed25519; pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=brookmangabriel@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762289518116158500 FEAT_MTE_TAGGED_FAR is a feature required for MTE4. The feature guarantees that the full address (including tag bits) is reported after a SEGV_MTESERR, and advertises itself in the ID_AA64PFR2_EL1 system register. QEMU was already reporting the full address, so this commit simply advertises the feature by setting that register, and unsets the register if MTE is disabled. Signed-off-by: Gabriel Brookman --- This patch is the first step toward implementing ARM's Enhanced Memory Tagging Extension (MTE4). MTE4 guarantees the presence of several subfeatures: FEAT_MTE_CANONICAL_TAGS, FEAT_MTE_TAGGED_FAR, FEAT_MTE_STORE_ONLY, FEAT_MTE_NO_ADDRESS_TAGS, and FEAT_MTE_PERM, none of which are currently implemented in QEMU. According to the ARM ARM, the presence of any of these features (except FEAT_MTE_PERM) implies the presence of all the others. For simplicity and ease of review, I plan to introduce them one at a time. This first patch focuses on FEAT_MTE_TAGGED_FAR. FEAT_MTE_TAGGED_FAR guarantees that the full fault address (including tag bits) is reported after a SEGV_MTESERR, and exposes itself in the ID_AA64PFR2_EL1 register. QEMU already reports the full address in this case, so this change only advertises the feature by setting the appropriate field in ID_AA64PFR2_EL1. The field is cleared when MTE support is disabled or rolled back to instruction-only. Testing: - Verified in system mode that the MTEFAR field in ID_AA64PFR2_EL1 is set to 1 when running with mte=3Don and cleared with mte=3Doff. - Verified in user mode test that SEGV_MTESERR faults report the full tagged address as expected. I didn=E2=80=99t include these checks as formal tests since the functionali= ty is simple, but I can add them in follow-up versions if reviewers prefer. Follow-up patches will implement the remaining MTE4 subfeatures listed above. Thanks, Gabriel Brookman --- target/arm/cpu.c | 4 +++- target/arm/tcg/cpu64.c | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 39292fb9bc..804e70b235 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2020,6 +2020,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) */ if (tcg_enabled() && cpu->tag_memory =3D=3D NULL) { FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); + FIELD_DP64_IDREG(isar, ID_AA64PFR2, MTEFAR, 0); } =20 /* @@ -2027,7 +2028,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * enabled on the guest (i.e mte=3Doff), clear guest's MTE bits." */ if (kvm_enabled() && !cpu->kvm_mte) { - FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR2, MTEFAR, 0); } #endif } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6871956382..27f0b43256 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1283,6 +1283,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ SET_IDREG(isar, ID_AA64PFR1, t); =20 + t =3D GET_IDREG(isar, ID_AA64PFR2); + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* FEAT_MTE_TAGGED_FAR= */ + SET_IDREG(isar, ID_AA64PFR2, t); + t =3D GET_IDREG(isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ --- base-commit: e9c692eabbbb7f395347605a6ef33a32d398ea25 change-id: 20251104-feat-mte-tagged-far-c8d302a888ad Best regards, --=20 Gabriel Brookman