From nobody Fri Nov 14 19:43:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762190030; cv=none; d=zohomail.com; s=zohoarc; b=DFXAJrlacGwsiqf+rv44aKQ+Ayej/mweIjJ8JJcQTeRSCfr/1Jv91t0ee3IwE2ly8I+tDwI+7LVC0biA9gGS6xmW3OgPlHNpNAaYOnCbafCd5Eh1lxO9E2nHolwYfdUGsBdrjgTPWcg62tU3FiW0aEhjA4pgKJyXkxlHeBuGooI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762190030; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=xzmt7cLSz4yJS8IzF79BoJ0z6M/UFl7qXf5BHQA55gk=; b=jKZD7ws+U6ztueKlQHaZneJ07Gc5EZP6O00+VjNIIRv1p38sbzCSol8bblK+rpBIQ+sDZ9J3nEA8h68PHoX3UI8pyxhvNzuXn/PRb5aDXtksHEIn0XY2MUqalStovMvNnPLQ3BzeKUnFEEaLKu7Xk78yT65UDLeiq61EVrd76E8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762190030025405.6211199335452; Mon, 3 Nov 2025 09:13:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vFy3g-0000SY-17; Mon, 03 Nov 2025 12:09:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy3e-0000SI-EF for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:30 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy3T-0000r8-2G for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=xzmt7cLSz4yJS8IzF79BoJ0z6M/UFl7qXf5BHQA55gk=; b=OpICEMA5rgSB8Te JABJ2IYWl3O84+3zcn+n3eupi1tEZR5nbgyIymcSdQkypr6cr/kRG07c2vQEoXqWCAypOJgkiJLTI 85k00KKT+yXpGLGWyW2J1w0+5vpwWxvJCEEkQffRXzRdK/3Zeo3lfmXNN3/Hf6oJoYF+fMGU1k+/8 Ks=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com, Anton Johansson Subject: [PATCH v5 03/25] target/riscv: Fix size of pc, load_[val|res] Date: Mon, 3 Nov 2025 18:11:46 +0100 Message-ID: <20251103171208.24355-4-anjo@rev.ng> In-Reply-To: <20251103171208.24355-1-anjo@rev.ng> References: <20251103171208.24355-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1762190036348158500 Content-Type: text/plain; charset="utf-8" Fix to 64 bits in size and as these are mapped to TCG globals, be careful with host endianness when allocating globals. Casts are added to logging expressions to retain the correct size for TARGET_RISCV32. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 6 +++--- target/riscv/machine.c | 6 +++--- target/riscv/translate.c | 12 +++++++----- 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd200ccad4..f00ae69e8a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -225,9 +225,9 @@ struct CPUArchState { uint8_t vxsat; bool vill; =20 - target_ulong pc; - target_ulong load_res; - target_ulong load_val; + uint64_t pc; + uint64_t load_res; + uint64_t load_val; =20 /* Floating-Point state */ uint64_t fpr[32]; /* assume both F and D extensions */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dc97d35458..353b927dd5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -528,7 +528,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s %d\n", "V =3D ", env->virt_enabled); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY { static const int dump_csrs[] =3D { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1f791e4de3..e105dec426 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2278,9 +2278,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 qemu_log_mask(CPU_LOG_INT, "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", " - "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=3D%= s\n", - __func__, env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); + "epc:0x%"PRIx64", tval:0x"TARGET_FMT_lx", desc=3D%s\n", + __func__, env->mhartid, async, cause, env->pc, + tval, riscv_cpu_get_trap_name(cause, async)); =20 mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 440b09fc32..66ed3f6504 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -433,9 +433,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), - VMSTATE_UINTTL(env.pc, RISCVCPU), - VMSTATE_UINTTL(env.load_res, RISCVCPU), - VMSTATE_UINTTL(env.load_val, RISCVCPU), + VMSTATE_UINT64(env.pc, RISCVCPU), + VMSTATE_UINT64(env.load_res, RISCVCPU), + VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINTTL(env.frm, RISCVCPU), VMSTATE_UINTTL(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 15eee7f6ee..e82805e178 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1459,6 +1459,10 @@ void riscv_translate_init(void) /* 32 bits in size, no offset needed */ size_t vl_offset =3D offsetof(CPURISCVState, vl); size_t vstart_offset =3D offsetof(CPURISCVState, vstart); + /* 64 bits in size mapped to TCGv, needs offset */ + size_t pc_offset =3D offsetof(CPURISCVState, pc) + field_offset; + size_t res_offset =3D offsetof(CPURISCVState, load_res) + field_off= set; + size_t val_offset =3D offsetof(CPURISCVState, load_val) + field_off= set; =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, @@ -1474,11 +1478,9 @@ void riscv_translate_init(void) offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); } =20 - cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); + cpu_pc =3D tcg_global_mem_new(tcg_env, pc_offset, "pc"); cpu_vl =3D tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); cpu_vstart =3D tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"= ); - load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), - "load_res"); - load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), - "load_val"); + load_res =3D tcg_global_mem_new(tcg_env, res_offset, "load_res"); + load_val =3D tcg_global_mem_new(tcg_env, val_offset, "load_val"); } --=20 2.51.0