From nobody Fri Nov 14 19:43:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762190102; cv=none; d=zohomail.com; s=zohoarc; b=JtZ+ty8Qpzp/0vHAgwnbD3FsqQIZ1AjoI2M0j3T3bn+EY3hDnM5ZVjl/7VB4lvGXtrEB/IsiaJGaCefOU6HFl3zlfkTTPr8KENpo2J28L7cTigGzAl3zZCuZWgFC3CqPtYyTnt/oHUuXlNyu+eAnjLr1UtGv+E1KYg5vCT+OJPA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762190102; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Ty7V6mUm7E7xW82v49FaJ5HOHnoOvuLwGtXFsf+RLyA=; b=OLuIgSka8mZoWyS54rkmMJAla/Z8kXXCYc5mWU+Ycxwhaz1ziuTNgE+255HQJHDFl52FZ6ttOHRuy0wtzj1P4irTCC19NavpDO3z/5HBDyCCyJZgis9fJ8lGy1FlkNoUU38c3ii7NRAIqYnLBF4um4truKc/nyhtfv3MEMmu2cc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762190102497444.2898132322364; Mon, 3 Nov 2025 09:15:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vFy3s-0000Wq-Gu; Mon, 03 Nov 2025 12:09:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy3r-0000WA-5k for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:43 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy3i-0000si-Jo for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Ty7V6mUm7E7xW82v49FaJ5HOHnoOvuLwGtXFsf+RLyA=; b=gyn0j9JPXyqaomj DnUcufYH21DTx5F14tF3Jjw5RT5X7oEUXpEf+P+rfatbg6UlEuG6dlqBYOV5AI5ONMMT5ESaDpa8z VWxBFUsVHPAaDu8yMmBjstK+LW+m/3254rbNc4E+bDtLBRBhFThN00RIaJRcvl/JjJ4rdG5YwYU0j Ns=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com, Anton Johansson Subject: [PATCH v5 14/25] target/riscv: Fix size of [m|s|vs]iselect fields Date: Mon, 3 Nov 2025 18:11:57 +0100 Message-ID: <20251103171208.24355-15-anjo@rev.ng> In-Reply-To: <20251103171208.24355-1-anjo@rev.ng> References: <20251103171208.24355-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1762190102758158501 Content-Type: text/plain; charset="utf-8" [m|s|vs]iselect are defined in version 20250508 of the privileged specification to be XLEN in size, however QEMU only ever uses at most 16 bits of these fields, so fix them to 16. Update relevant function arguments. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/csr.c | 32 ++++++++++++++++---------------- target/riscv/machine.c | 6 +++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f051796f4..b35851cf4f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -343,8 +343,8 @@ struct CPUArchState { uint8_t siprio[64]; =20 /* AIA CSRs */ - target_ulong miselect; - target_ulong siselect; + uint16_t miselect; + uint16_t siselect; uint64_t mvien; uint64_t mvip; =20 @@ -390,7 +390,7 @@ struct CPUArchState { uint64_t vsatp; =20 /* AIA VS-mode CSRs */ - target_ulong vsiselect; + uint16_t vsiselect; =20 uint64_t mtval2; uint64_t mtinst; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1c6797ca8d..a29edbb369 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2398,7 +2398,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env= , int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - target_ulong *iselect; + uint16_t *iselect; int ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); @@ -2441,18 +2441,18 @@ static RISCVException rmw_xiselect(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static bool xiselect_aia_range(target_ulong isel) +static bool xiselect_aia_range(uint16_t isel) { return (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) || (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST); } =20 -static bool xiselect_cd_range(target_ulong isel) +static bool xiselect_cd_range(uint16_t isel) { return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST); } =20 -static bool xiselect_ctr_range(int csrno, target_ulong isel) +static bool xiselect_ctr_range(int csrno, uint16_t isel) { /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */ return CTR_ENTRIES_FIRST <=3D isel && isel <=3D CTR_ENTRIES_LAST && @@ -2460,7 +2460,7 @@ static bool xiselect_ctr_range(int csrno, target_ulon= g isel) } =20 static int rmw_iprio(target_ulong xlen, - target_ulong iselect, uint8_t *iprio, + uint16_t iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, target_ulong wr_mask, int ext_irq_no) { @@ -2504,7 +2504,7 @@ static int rmw_iprio(target_ulong xlen, return 0; } =20 -static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong *= val, target_ulong new_val, target_ulong wr_mask) { /* @@ -2543,7 +2543,7 @@ static int rmw_ctrsource(CPURISCVState *env, int isel= , target_ulong *val, return 0; } =20 -static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong *= val, target_ulong new_val, target_ulong wr_mask) { /* @@ -2582,7 +2582,7 @@ static int rmw_ctrtarget(CPURISCVState *env, int isel= , target_ulong *val, return 0; } =20 -static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *va= l, target_ulong new_val, target_ulong wr_mask) { /* @@ -2623,7 +2623,7 @@ static int rmw_ctrdata(CPURISCVState *env, int isel, = target_ulong *val, } =20 static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { bool virt =3D false, isel_reserved =3D false; @@ -2703,12 +2703,12 @@ done: } =20 static int rmw_xireg_cd(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { int ret =3D -EINVAL; - int ctr_index =3D isel - ISELECT_CD_FIRST; - int isel_hpm_start =3D ISELECT_CD_FIRST + 3; + uint16_t ctr_index =3D isel - ISELECT_CD_FIRST; + uint16_t isel_hpm_start =3D ISELECT_CD_FIRST + 3; =20 if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_sscc= fg) { ret =3D RISCV_EXCP_ILLEGAL_INST; @@ -2775,7 +2775,7 @@ done: } =20 static int rmw_xireg_ctr(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) { @@ -2803,7 +2803,7 @@ static int rmw_xireg_ctr(CPURISCVState *env, int csrn= o, * extension using csrind should be implemented here. */ static int rmw_xireg_csrind(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false; @@ -2833,7 +2833,7 @@ static int rmw_xiregi(CPURISCVState *env, int csrno, = target_ulong *val, target_ulong new_val, target_ulong wr_mask) { int ret =3D -EINVAL; - target_ulong isel; + uint16_t isel; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); if (ret !=3D RISCV_EXCP_NONE) { @@ -2864,7 +2864,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, i= nt csrno, target_ulong wr_mask) { int ret =3D -EINVAL; - target_ulong isel; + uint16_t isel; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); if (ret !=3D RISCV_EXCP_NONE) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8a8f5be8d6..376075b2bd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINT64(env.vscause, RISCVCPU), VMSTATE_UINT64(env.vstval, RISCVCPU), VMSTATE_UINT64(env.vsatp, RISCVCPU), - VMSTATE_UINTTL(env.vsiselect, RISCVCPU), + VMSTATE_UINT16(env.vsiselect, RISCVCPU), VMSTATE_UINT64(env.vsie, RISCVCPU), =20 VMSTATE_UINT64(env.mtval2, RISCVCPU), @@ -467,8 +467,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mepc, RISCVCPU), VMSTATE_UINT64(env.mcause, RISCVCPU), VMSTATE_UINT64(env.mtval, RISCVCPU), - VMSTATE_UINTTL(env.miselect, RISCVCPU), - VMSTATE_UINTTL(env.siselect, RISCVCPU), + VMSTATE_UINT16(env.miselect, RISCVCPU), + VMSTATE_UINT16(env.siselect, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU), VMSTATE_UINT32(env.mcounteren, RISCVCPU), VMSTATE_UINT32(env.scountinhibit, RISCVCPU), --=20 2.51.0