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Signed-off-by: Bernhard Beschow Message-id: 20251101120130.236721-2-shentey@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 19 +++++++++++++++++++ hw/arm/fsl-imx8mp.c | 34 +++++++++++++++++++++++++++++----- hw/arm/imx8mp-evk.c | 11 +++++++++++ hw/arm/Kconfig | 3 ++- 4 files changed, 61 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index b2f7d29ade5..75c8fbd3668 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -60,3 +60,22 @@ Now that everything is prepared the machine can be start= ed as follows: -dtb imx8mp-evk.dtb \ -append "root=3D/dev/mmcblk2p2" \ -drive file=3Dsdcard.img,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmcblk2 + + +KVM Acceleration +---------------- + +To enable hardware-assisted acceleration via KVM, append +``-accel kvm -cpu host`` to the command line. While this speeds up perform= ance +significantly, be aware of the following limitations: + +* The ``imx8mp-evk`` machine is not included under the "virtualization use= case" + of :doc:`QEMU's security policy `. This means that you + should not trust that it can contain malicious guests, whether it is run + using TCG or KVM. If you don't trust your guests and you're relying on Q= EMU to + be the security boundary, you want to choose another machine such as ``v= irt``. +* Rather than Cortex-A53 CPUs, the same CPU type as the host's will be use= d. + This is a limitation of KVM and may not work with guests with a tight + dependency on Cortex-A53. +* No EL2 and EL3 exception levels are available which is also a KVM limita= tion. + Direct kernel boot should work but running U-Boot, TF-A, etc. won't succ= eed. diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 866f4d1d740..ee6f3e42d23 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -12,11 +12,13 @@ #include "system/address-spaces.h" #include "hw/arm/bsa.h" #include "hw/arm/fsl-imx8mp.h" -#include "hw/intc/arm_gicv3.h" #include "hw/misc/unimp.h" #include "hw/boards.h" +#include "system/kvm.h" #include "system/system.h" +#include "target/arm/cpu.h" #include "target/arm/cpu-qom.h" +#include "target/arm/kvm_arm.h" #include "qapi/error.h" #include "qobject/qlist.h" =20 @@ -193,15 +195,15 @@ static void fsl_imx8mp_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); FslImx8mpState *s =3D FSL_IMX8MP(obj); + const char *cpu_type =3D ms->cpu_type ?: ARM_CPU_TYPE_NAME("cortex-a53= "); int i; =20 for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX8MP_NUM_CPUS); i++) { g_autofree char *name =3D g_strdup_printf("cpu%d", i); - object_initialize_child(obj, name, &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a53")); + object_initialize_child(obj, name, &s->cpu[i], cpu_type); } =20 - object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3); + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); =20 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM); =20 @@ -274,7 +276,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) /* CPUs */ for (i =3D 0; i < ms->smp.cpus; i++) { /* On uniprocessor, the CBAR is set to 0 */ - if (ms->smp.cpus > 1) { + if (ms->smp.cpus > 1 && + object_property_find(OBJECT(&s->cpu[i]), "reset-cbar")) { object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST]= .addr, &error_abort); @@ -286,6 +289,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, &error_abort); =20 + if (object_property_find(OBJECT(&s->cpu[i]), "has_el2")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el2", + !kvm_enabled(), &error_abort); + } + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", + !kvm_enabled(), &error_abort); + } + if (i) { /* * Secondary CPUs start in powered-down state (and can be @@ -304,6 +317,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) { SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); QList *redist_region_count; + bool pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NU= LL); =20 qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus); qdev_prop_set_uint32(gicdev, "num-irq", @@ -360,6 +374,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + if (kvm_enabled()) { + if (pmu) { + assert(arm_feature(&s->cpu[i].env, ARM_FEATURE_PMU)); + if (kvm_irqchip_in_kernel()) { + kvm_arm_pmu_set_irq(&s->cpu[i], VIRTUAL_PMU_IRQ); + } + kvm_arm_pmu_init(&s->cpu[i]); + } + } } } =20 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index fc880a1d44b..3ddcf1af5ac 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -13,6 +13,7 @@ #include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "system/kvm.h" #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -94,12 +95,22 @@ static void imx8mp_evk_init(MachineState *machine) } } =20 +static const char *imx8mp_evk_get_default_cpu_type(const MachineState *ms) +{ + if (kvm_enabled()) { + return ARM_CPU_TYPE_NAME("host"); + } + + return ARM_CPU_TYPE_NAME("cortex-a53"); +} + static void imx8mp_evk_machine_init(MachineClass *mc) { mc->desc =3D "NXP i.MX 8M Plus EVK Board"; mc->init =3D imx8mp_evk_init; mc->max_cpus =3D FSL_IMX8MP_NUM_CPUS; mc->default_ram_id =3D "imx8mp-evk.ram"; + mc->get_default_cpu_type =3D imx8mp_evk_get_default_cpu_type; } =20 DEFINE_MACHINE_AARCH64("imx8mp-evk", imx8mp_evk_machine_init) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b44b85f4361..0cdeb60f1f2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -622,7 +622,8 @@ config FSL_IMX8MP config FSL_IMX8MP_EVK bool default y - depends on TCG && AARCH64 + depends on AARCH64 + depends on TCG || KVM select FSL_IMX8MP =20 config ARM_SMMUV3 --=20 2.43.0 From nobody Sun Nov 16 01:15:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1762184903; cv=none; d=zohomail.com; s=zohoarc; b=VjQpdrrDooQX2YN7NEgvv/Q+ydWifLtrHaa6EXRX8NZiQ2WrLpH1KXypBe8x5+GyS4ZT6WZz9lQKtECxiFDeJnzJJREOI4Wk1qDxKYzeyB6kQQGQSY+86gji75ieRQ5wIeRMTOFK8zMzVCCqL8nH2uI7VLJloL3Kan3HKYuYx+Y= ARC-Message-Signature: i=1; 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In KVM mode, the host CPU is used whose system counter runs at a different frequency, resulting in the guest clock running slower or faster. Fix this by not hardcoding the clock frequency which makes the Linux driver read the real clock frequency from the register. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Bernhard Beschow Message-id: 20251101120130.236721-3-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/arm/imx8mp-evk.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 3ddcf1af5ac..44e06019670 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -44,6 +44,15 @@ static void imx8mp_evk_modify_dtb(const struct arm_boot_= info *info, void *fdt) fdt_nop_property(fdt, offset, "cpu-idle-states"); offset =3D fdt_node_offset_by_compatible(fdt, offset, "arm,cortex-= a53"); } + + if (kvm_enabled()) { + /* Use system counter frequency from host CPU to fix time in guest= */ + offset =3D fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer= "); + while (offset >=3D 0) { + fdt_nop_property(fdt, offset, "clock-frequency"); + offset =3D fdt_node_offset_by_compatible(fdt, offset, "arm,arm= v8-timer"); + } + } } =20 static void imx8mp_evk_init(MachineState *machine) --=20 2.43.0 From nobody Sun Nov 16 01:15:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1762184957; cv=none; d=zohomail.com; s=zohoarc; b=JPxjuxvxkBBtxvQXaS+AKZMtDfTOns45aVbyfP+3tD54/jUqY2u3az5ER3Bcp7y1JllI9AnckQiAFh3rlhc2IZtzhR1bqRj/3fwmVOUadpgDg176sFCm0XZ5DzCYInAAUS1EhFfToac4jmv8Tj77vc8yUTgExoVdlF1h9QtoVxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762184957; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hAwSv5m0SCHS7ZUiqLQkSHrP57WMiWiuegLNWilDi8Y=; b=Hdw7lKNL5ysO7EER3eQ+vegjoxIS3pQQnsTubj91I1sD3xdl1eiqmigqcPKNdxwc7zVjnOXMRX8S8/etCDrxxmKGY48KjkCDlfbwl0LoenLRzZCFmYysaW8abGrjjtGy5Ew9QQYV8Vf4gtA1Hn98m8o+8fI8QzoJ/UMGpGOZRWo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762184957421799.5083975559959; Mon, 3 Nov 2025 07:49:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vFwmA-0005Br-E1; Mon, 03 Nov 2025 10:47:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFwm8-0005B5-Ak for qemu-devel@nongnu.org; Mon, 03 Nov 2025 10:47:20 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vFwlx-0002ip-46 for qemu-devel@nongnu.org; Mon, 03 Nov 2025 10:47:20 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-421851bca51so3984562f8f.1 for ; Mon, 03 Nov 2025 07:47:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429ce6b0c16sm10504156f8f.38.2025.11.03.07.47.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 07:47:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1762184825; x=1762789625; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hAwSv5m0SCHS7ZUiqLQkSHrP57WMiWiuegLNWilDi8Y=; b=E4PDAE0endaWC2bqSoySSklGcgCZnBB71abcFqBwCUCETOBdhsxZ8GohwMqXjk5Qy4 ZXkBU8uHcsE/tH+IRsNADoY6Z7z18xiymnddWUG8bMmTtGlBNDXac74EEohmjlwxfMgt /aJ6cy/pWAQtPkRKTjQ0mvQYBAe34NY3bjb13sT4xAeedeObSoF5d7+UtxvMiilGRlcQ DinAyNf2I3sM5KJwRRHwOeGGxMSN8VCzRBgBhKxrQyCZMe1m/RiJJKKQOlE4x0qD12Ex /HcRFoiBwwNhZa8hqeXtXE54pQPnDv8sl4jFxsjz2MtILjpAEgnXL1PM8j+K2NRpx018 Gu3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762184825; x=1762789625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hAwSv5m0SCHS7ZUiqLQkSHrP57WMiWiuegLNWilDi8Y=; b=kXGieXlCoSTVjaev3YT4ACLzkM1xw7p8cjsDirN0M+vPUKfZMtG5RmuLlIkONDyV4s IKNWboX0ytMY1U/CFBdBa8PLIfWAx6iXjaXgk1Dwq5XRYsDlhFYA6TXNmz4d130xUb9H jDBJ98xYbe+FazNBhdzSfVANUvtxEZ2B1Sb4WNdUYm1NOmuIJh+u/ONW7sHCYLbz2tfv jx3Ofd5/p94WhFIqTHl8PvGyHwWTusK9dK0Xg11QjBEivuhakh0WdeufT3k4IK60pV1V Fs8bZUARIG2An4joS4qsVZh2PY3WmghgpZxbUhc856Ahsmsxoj+w9+PWcSghcqsT7PE/ 2RvQ== X-Gm-Message-State: AOJu0Yxev6T4ACUghPyfYODBYxSWQUaBAJwYQCM4zrwXG9bMq2CAXmtq 8UuXQpnRK6fxHCljP0lCbHRc9FPIlxCQHvZq2HzBfKxJNkRzTot9Wf3fgM0acsOZfA1oj9oDCkG NtSC/ X-Gm-Gg: ASbGncuHISyWxOZlF9SAsBjYkmRWQQ29178fR/9ZoxjccoE8qh/AKog3HcVqcVePC5B wLxS8ILpd5C+kxhm8w+FhzSpWYoD46WvExb81K+IkHjzZGSMcsI16FR9ig86Owlc+sl6RMMqmO5 T6ss/z1Ll8en1L2ao1gWO6RO7RNuQzs+IIFzLPmJ1PGf7YcgyKlaZIhxXRANUmYlznTUiTXq78r PhdK5B8HGZ7AFXKi6r1wP0lqM/bPR/XMaCSvtPDVxEeZufIlmvGcWpxSvVPQWNYmEy0ZLxxGrGs DA4d9yWe41PIhBQSnM8oIYj4NViHMLwK8UUSSS+YkpsILt7NvT20dFucJQllw9rPRJUT13HxOYS hEfyrwyvghxBtqWrnCbi5/KT9AHTEj0FE75yzpvkjxUWXMa1GBY8kIJSLxT/4b9ZyfgAsf/zkFU jwKySc02wBwmeGW+rm X-Google-Smtp-Source: AGHT+IEuJAQhMZuavzQE31Va/eF6pd1l+rlSPxtlK0wBMqMqyRxzIcdjUvF/10N5Sh8N1OuWbbWCDQ== X-Received: by 2002:a05:6000:4312:b0:429:ce81:fe0d with SMTP id ffacd0b85a97d-429ce82001emr4650123f8f.60.1762184825220; Mon, 03 Nov 2025 07:47:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/3] docs/devel/testing/fuzzing: Note that you can get qtest to read from a file Date: Mon, 3 Nov 2025 15:47:00 +0000 Message-ID: <20251103154700.4126379-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251103154700.4126379-1-peter.maydell@linaro.org> References: <20251103154700.4126379-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1762184959537154100 Content-Type: text/plain; charset="utf-8" It is possible to get qtest to read fuzzer reproducers from a file rather than directly from stdio; this is useful when you want to run QEMU under gdb to debug the failure. Document how to do this, which was previously only written down in the commit message for 5b18a6bf44b9 ("chardev: Allow setting file chardev input file on the command line"). Signed-off-by: Peter Maydell Reviewed-by: Fabiano Rosas Reviewed-by: Manos Pitsidianakis Message-id: 20251028165236.3327658-1-peter.maydell@linaro.org --- docs/devel/testing/fuzzing.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/docs/devel/testing/fuzzing.rst b/docs/devel/testing/fuzzing.rst index c3ac084311b..c43f815f320 100644 --- a/docs/devel/testing/fuzzing.rst +++ b/docs/devel/testing/fuzzing.rst @@ -263,6 +263,15 @@ generic-fuzz target. =20 - Report the bug and send a patch with the C reproducer upstream =20 +QEMU can also read the reproducer directly from a file rather than +from standard input:: + + $QEMU_PATH $QEMU_ARGS -qtest chardev:repro \ + -chardev file,id=3Drepro,path=3D/dev/null,input-path=3D/tmp/reproduc= er + +This is useful if you want to run QEMU under a debugger to investigate +the failure. + Implementation Details / Fuzzer Lifecycle ----------------------------------------- =20 --=20 2.43.0