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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1762167559; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cbh68C6fmQ5R1KcYwKeBdnUQDfSG4HCjvnxl+QuCZ4I=; b=SCwZEldhre3MQ+78PLwAZlQsI8HTz+wSeH3Suwb51abst9+TH1C9+rZw6/6L4PeHGG1ipv HjtHXl2pB77L+TelorX72IgEQpghAhywv4lKCVk64P+9s2/qIAbUjV53nwrSoycGa4tovM RDKXicuCY26tFYewnwbuJjTUcYZ7zZ4= X-MC-Unique: YvLVsSD2NAujAWMC1IL9_w-1 X-Mimecast-MFC-AGG-ID: YvLVsSD2NAujAWMC1IL9_w_1762167554 From: Thomas Huth To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Heiko Carstens , qemu-stable@nongnu.org, Ilya Leoshkevich Subject: [PULL 21/22] target/s390x: Use address generation for register branch targets Date: Mon, 3 Nov 2025 11:58:18 +0100 Message-ID: <20251103105824.322039-22-thuth@redhat.com> In-Reply-To: <20251103105824.322039-1-thuth@redhat.com> References: <20251103105824.322039-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1762167666122158500 From: Ilya Leoshkevich Indirect branches to addresses taken from registers go through address generation, e.g., for BRANCH ON CONDITION Principles of Operation says: In the RR format, the contents of general register R2 are used to generate the branch address QEMU uses r2_nz handler for the respective register operands. Currently it does not zero out extra bits in 24- and 31-bit addressing modes as required by address generation. The very frequently used s390x_tr_init_disas_context() function has a workaround for this, but the code for saving an old PSW during an interrupt does not. Add the missing masking to r2_nz. Enforce PSW validity by replacing the workaround with an assertion. Reported-by: Thomas Wei=C3=9Fschuh Reported-by: Heiko Carstens Link: https://lore.kernel.org/lkml/ab3131a2-c42a-47ff-bf03-e9f68ac053c0@t-8= ch.de/ Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich Tested-by: Thomas Wei=C3=9Fschuh Message-ID: <20251016175954.41153-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth --- target/s390x/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index ec9e5a07516..4d2b8c5e2be 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5613,6 +5613,7 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o) int r2 =3D get_field(s, r2); if (r2 !=3D 0) { o->in2 =3D load_reg(r2); + gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); } } #define SPEC_in2_r2_nz 0 @@ -6379,10 +6380,12 @@ static void s390x_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &=3D 0x7fffffff; - dc->base.pc_next =3D dc->base.pc_first; + if (dc->base.tb->flags & FLAG_MASK_32) { + if (!(dc->base.tb->flags & FLAG_MASK_64)) { + assert(!(dc->base.pc_first & ~((1ULL << 31) - 1))); + } + } else { + assert(!(dc->base.pc_first & ~((1ULL << 24) - 1))); } =20 dc->cc_op =3D CC_OP_DYNAMIC; --=20 2.51.0