From nobody Sun Nov 16 02:28:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762162290; cv=none; d=zohomail.com; s=zohoarc; b=EtEjw/H1wrXRVy22YNyeiZawWoxte2a25Wi+fsg90i81Ajyh+c8hMxXbojEmL7ccoavwXuHtZxfOVAp9GA3c2MVDfxxLp1599ZyaSfu4R7O6QNH+0WlNb0jUttq/9aH8IQ/k8MglATky0gmEAEEH4ww5CJm9ctbckcR9kM08zgc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762162290; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=lSxyVwSAHfVgZ7ICi8d1pW3YkaSnw1oD14AqpaBT1T4=; b=QPIx8QRJ2EwoIvuwfMkHOg7s6pMEoBB6O00Aw2e8tON/+ycMja9g641baQ9XJ+idVUFA6H4joS7183xXHXndZBMtj2uIHLwGdzHLe2Ig93jXO2BxBanlU3jRyeQR48hVtIqzgW+36MkNTTgpFYkTpEQ4CfnEcY6Z0vb5tJrSmsQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762162290644831.7722441259308; Mon, 3 Nov 2025 01:31:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vFqs7-0000vE-Aw; Mon, 03 Nov 2025 04:29:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFqs4-0000uT-Ly; Mon, 03 Nov 2025 04:29:04 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFqs1-0001r9-Og; Mon, 03 Nov 2025 04:29:04 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 3 Nov 2025 17:28:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 3 Nov 2025 17:28:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v3 12/30] hw/arm/aspeed: Split Supermicro X11SPI machine into a separate file for maintainability Date: Mon, 3 Nov 2025 17:27:23 +0800 Message-ID: <20251103092801.1282602-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251103092801.1282602-1-jamin_lin@aspeedtech.com> References: <20251103092801.1282602-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762162294561158500 This commit moves the Supermicro X11SPI BMC machine definition from aspeed.c into a new standalone file aspeed_ast2500_supermicro-x11spi.c, and adds a dedicated I=C2=B2C initialization function for the platform. The refactor continues the effort to modularize Aspeed platform support, ensuring each machine model is defined in its own source file. This improves code organization, readability, and simplifies maintenance when adding or modifying platform-specific behavior. Previously, the Supermicro X11SPI machine reused palmetto_bmc_i2c_init() for its I=C2=B2C setup. To make the machine definition fully self-contained, the function was copied and renamed to supermicro_x11spi_bmc_i2c_init(). This ensures that the machine can evolve independently without depending on Palmetto=E2=80=99s board logi Key updates include: - Moved SUPERMICRO_X11SPI_BMC_HW_STRAP1 macro and machine class init (aspeed_machine_supermicro_x11spi_bmc_class_init) into a new file. - Added new function supermicro_x11spi_bmc_i2c_init() copied from palmetto_bmc_i2c_init() for independent control. - Updated the machine definition to use the new I=C2=B2C init function. - Registered the new source file in meson.build. - Removed all Supermicro X11SPI-related definitions from aspeed.c. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 33 ---------- hw/arm/aspeed_ast2500_supermicro-x11spi.c | 78 +++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 79 insertions(+), 33 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_supermicro-x11spi.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31b281f55..e1fa95b2c3 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -71,16 +71,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) =20 -/* TODO: Find the actual hardware value */ -#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ - AST2500_HW_STRAP1_DEFAULTS | \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_SPI_WIDTH | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) - /* AST2500 evb hardware value: 0xF100C2E6 */ #define AST2500_EVB_HW_STRAP1 (( \ AST2500_HW_STRAP1_DEFAULTS | \ @@ -1187,24 +1177,6 @@ static void aspeed_machine_supermicrox11_bmc_class_i= nit(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } =20 -static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, - const void *da= ta) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Supermicro X11 SPI BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D SUPERMICRO_X11SPI_BMC_HW_STRAP1; - amc->fmc_model =3D "mx25l25635e"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 1; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init =3D palmetto_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, const void *data) { @@ -1577,11 +1549,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_supermicrox11_bmc_class_init, .interfaces =3D arm_machine_interfaces, - }, { - .name =3D MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_supermicro_x11spi_bmc_class_init, - .interfaces =3D arm_machine_interfaces, }, { .name =3D MACHINE_TYPE_NAME("ast2500-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2= 500_supermicro-x11spi.c new file mode 100644 index 0000000000..bc3023f534 --- /dev/null +++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c @@ -0,0 +1,78 @@ +/* + * Supermicro X11 SPI + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/machines-qom.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" + +/* TODO: Find the actual hardware value */ +#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) + +static void supermicro_x11spi_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + DeviceState *dev; + uint8_t *eeprom_buf =3D g_malloc0(32 * 1024); + + /* + * The palmetto platform expects a ds3231 RTC but a ds1338 is + * enough to provide basic RTC features. Alarms will be missing + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x= 68); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, + eeprom_buf); + + /* add a TMP423 temperature sensor */ + dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2= ), + "tmp423", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_ab= ort); +} + +static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, + const void *da= ta) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Supermicro X11 SPI BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D SUPERMICRO_X11SPI_BMC_HW_STRAP1; + amc->fmc_model =3D "mx25l25635e"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 1; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init =3D supermicro_x11spi_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast2500_supermicro_x11spi_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_supermicro_x11spi_bmc_class_init, + .interfaces =3D arm_machine_interfaces, + } +}; + +DEFINE_TYPES(aspeed_ast2500_supermicro_x11spi_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index ff6a856523..76a456c33f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -48,6 +48,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_romulus.c', 'aspeed_ast2500_sonorapass.c', + 'aspeed_ast2500_supermicro-x11spi.c', 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2500_witherspoon.c', 'aspeed_ast2500_yosemitev2.c', --=20 2.43.0