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[90.33.190.31]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429c13e16f4sm5639277f8f.27.2025.10.31.14.20.07 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 31 Oct 2025 14:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1761945608; x=1762550408; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TRkWFU/aapO0FF6y9Y4J4SN7vpy3bH8aWYMTVG70Hn8=; b=IkTlWL1z3PVjSKCJeaqvDUIsu38aEd7FI60q3RN127YVMnqsytGzNQzX7HkiNV5PGf 9AS7NrZ5+g794PeZQMJdtAMmghiloMthvZAHzS3nW1XwVS4PbrD9ELrMAp4t68DPDzgw aIx3/DQJYAk9wMN8yiBYzQYo3+QxFxQyGl6jj/D814CD42IASlB2G6HKEf/nldnQ5D5s lHUWMWlxCj0bziRboCsC32z2jugb7CmrKmF8FApDrUc3uGWtkr3uIOa12mulK4YWKDD0 KJuRCiMzs9jn9M9WWF8UHZLQN/Mzu9vPT3D+MeauJo4nDX+kHblHbYY0tdxBEH3YutR3 V5FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761945608; x=1762550408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TRkWFU/aapO0FF6y9Y4J4SN7vpy3bH8aWYMTVG70Hn8=; b=Vssx/nZXPv8asu+yM2GMS1yUv0O+4hjD3Zd0gcLNlaRZCxBN0fdbtKEgYouZ2h/dKv lkM/F48Ef+q8d036TSz9o6jxyV2p94r0KhTfzhDGTwRDPBWa6eaPF/k4eiTSWOG2eQhs 9oIslRLytWDKn3EW6uBjmpwvMNsodd7EuGP//SH2KVHd1aSjVxOMMHKFkEhnQFlI4ZP0 r8tUPB5kvlNnoBFggPQYgmGsQW1yNtbqdzuw8/UTCE2/np3IKa0V0PPVI/TA55VCtGJG JX6XsgWRtq2M3sAwHqr/88ExLyhJ/XvvuvpdqMf8kZ96VZ//oVLLsgCXMUhtQ5kPYmBn q/+Q== X-Gm-Message-State: AOJu0YxDuu/lRgI1U/5Wd3FcwminiUzGwDMYi3meOaaEZZxbKwknem2U FLoP3Hff30/xwOUl/DhCu20BxaAOmWyb2nw3xfkl7EiLpP6yNPnDolUxiDeRMCWBJqXJzPe0qj1 jUj/9mfrKkg== X-Gm-Gg: ASbGnctLEJ9gnAUedccr83j/Z1EsVO5Or5Jj4iGeclkephqLwZ+ZXzhmwl7D6Tysj7s XIvqwhruJGQCgSYcvkRJb3tB4DuGTuPP9Ym/wv70nE+ct7nXt8tXav+HISQIB6lPcXb+n0VtKWG JsQFH4zuD/nLFrlHHbGqAfS9QTEdVU0jwqBGc5wVjPPAzasSJcUIn5ZBMl512JGRploHYMXH3al EQwAtQMO9Znnj6D9bQyuv4OKaZn6dnESpIUCVViEyOjwVV2J70o0db0bfEI89AwagtttJQxNrTB KDyMwwhASdj/bVzif8tAun6nl2BWKRxVlYXuxU2GcnLmsySkTvGgs76apJR0N4pbGWMbBzREsHW VDCiD7U50zlWLKZ9gFncXuAuf516+7wg8nSDdlArxd4QNS2ieICfyy7QFZFc1MTAu1xlEyMvSs9 f2PyqwaKu8sI21dOhK4Q5zPBgQmqEXSYL3MXr9oTqPW3H6HNoV X-Google-Smtp-Source: AGHT+IEcvUahVrXqdQpda5Jmzh00TDRKdk7K7n7yUy3kWYWRimLq4lodPyYuNRcgonQioDY8GNflkA== X-Received: by 2002:a05:6000:1acb:b0:425:75c6:7125 with SMTP id ffacd0b85a97d-429bd680bb9mr4527610f8f.16.1761945608366; Fri, 31 Oct 2025 14:20:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 9/9] rx: cpu: fix interrupts check in rx_cpu_do_interrupt() Date: Fri, 31 Oct 2025 22:15:18 +0100 Message-ID: <20251031211518.38503-10-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251031211518.38503-1-philmd@linaro.org> References: <20251031211518.38503-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761945646979154100 From: Igor Mammedov Commit 87511341c30 broke interrupt handling, replacing interrupts fetch with a bool and then the remaining code attempting to check individual bits on that bool value, which effectively masked those interrupts. Fix it by checking individual interrupt bits directly instead of old 'fetch then check' approach. Fixes: 87511341c30d ("add cpu_test_interrupt()/cpu_set_interrupt() helpers = and use them tree wide") Reported-by: Thomas Huth Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Thomas Huth Reviewed-by: Thomas Huth Message-ID: <20251030165932.138512-1-imammedo@redhat.com> [PMD: Rebased on commit dde21df2393 "call plugin trap callbacks"] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/helper.c | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target/rx/helper.c b/target/rx/helper.c index ef47e32add8..e9a7aaf610d 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -41,11 +41,9 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, in= t rte) env->psw_c =3D FIELD_EX32(psw, PSW, C); } =20 -#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { CPURXState *env =3D cpu_env(cs); - int do_irq =3D cpu_test_interrupt(cs, INT_FLAGS); uint32_t save_psw; uint64_t last_pc =3D env->pc; =20 @@ -59,29 +57,26 @@ void rx_cpu_do_interrupt(CPUState *cs) save_psw =3D rx_cpu_pack_psw(env); env->psw_pm =3D env->psw_i =3D env->psw_u =3D 0; =20 - if (do_irq) { - if (do_irq & CPU_INTERRUPT_FIR) { - env->bpc =3D env->pc; - env->bpsw =3D save_psw; - env->pc =3D env->fintv; - env->psw_ipl =3D 15; - cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); - qemu_set_irq(env->ack, env->ack_irq); - qemu_plugin_vcpu_interrupt_cb(cs, last_pc); - qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); - } else if (do_irq & CPU_INTERRUPT_HARD) { - env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); - env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); - env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); - env->psw_ipl =3D env->ack_ipl; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - qemu_set_irq(env->ack, env->ack_irq); - qemu_plugin_vcpu_interrupt_cb(cs, last_pc); - qemu_log_mask(CPU_LOG_INT, - "interrupt 0x%02x raised\n", env->ack_irq); - } + if (cpu_test_interrupt(cs, CPU_INTERRUPT_FIR)) { + env->bpc =3D env->pc; + env->bpsw =3D save_psw; + env->pc =3D env->fintv; + env->psw_ipl =3D 15; + cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); + qemu_set_irq(env->ack, env->ack_irq); + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); + } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { + env->isp -=3D 4; + cpu_stl_data(env, env->isp, save_psw); + env->isp -=3D 4; + cpu_stl_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); + env->psw_ipl =3D env->ack_ipl; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + qemu_set_irq(env->ack, env->ack_irq); + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_i= rq); } else { uint32_t vec =3D cs->exception_index; const char *expname =3D "unknown exception"; --=20 2.51.0