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Signed-off-by: Mohamed Mediouni Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d13ccf5508c..890e9266f93 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -763,6 +763,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) hv_vcpu_t fd; hv_return_t r =3D HV_SUCCESS; hv_vcpu_exit_t *exit; + uint64_t t; int i; =20 ahcf->dtb_compatible =3D "arm,armv8"; @@ -781,9 +782,19 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) for (i =3D 0; i < ARRAY_SIZE(regs); i++) { r |=3D hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); } - r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); r |=3D hv_vcpu_destroy(fd); =20 + /* + * Hardcode MIDR because Apple deliberately doesn't expose a divergent + * MIDR across systems. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0x61); /* Apple */ + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); /* v7 or later */ + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 0); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + ahcf->midr =3D t; + clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 /* --=20 2.43.0