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[195.35.155.187]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b7077975dcbsm158078366b.14.2025.10.31.04.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 04:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1761911617; x=1762516417; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GU0Gskq9M+nEhWLhMqv07GFwmNCHtS491c2/qibObY8=; b=XBz6VtIMzjbsrY6/RXa+ydGqaoRgQKk4jsJUVm1DRRfVfkd2JqjqcImuBGJMwx3+cm 9WvvcMtyl4qw17CIRdFy2AR8PyaCmW5HVgixPXp7A+otT0pUnxmKDbmp7kFCysPRI+DE ylB0X6qE2+/41tgM6eThEmteRjA7gvf5N7vWvPmCl5FKNCX9sECBr2RrOSl3snQcjATc SKGtIPpm9SZBi0nKpFWOSjWDvRapp6RPkMYtqff4rocL2oAsyWaR039cxQ8zCFgGJguR w1fsqxEDYTb1/1RYP5RGtzo7N1drC8igzdSIU6a1QCcjcUQqD265LdC13zIKoPxzldyW u0Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761911617; x=1762516417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GU0Gskq9M+nEhWLhMqv07GFwmNCHtS491c2/qibObY8=; b=Bhjj6p5r+uMLf/rJawa0sBN3Pq0rdBkP3i/hEhXg8uy53bKgZjZudETRQeG6LBlmJW JBDv6QhmDy7OEMBidx/LXrHFUBgh/Taa2zRkU+0hHBV6jtPdgl+e+ssEz7GGyDB8bx5B Ra0qKDJL0d906MBAzJxK4lmrxeNvmDzk9WBB+4GRtzra0H4SPg7K1C1uUkSJjN0sgH9B vOjMiwDTUepPz4lrs8RrjJ2IArDaDyG2i3tps4yWMEt43XGUM5XZ8RhAgT/JPtAXfm3o kvmT/dADSIA+RgprHOrWOa2n5z8anpDYHpbq1558G/erQWh19LeWS+yy6xfPOd1WPquy 3lQQ== X-Gm-Message-State: AOJu0Yyxc5UIFxjASSPV6IHD9DWNJE+Iwrd0oKBPytzaGF2RoTFy6e4b 5I3MqZuIZnwHZyEGA1ti55MC5AgG1J8DZInZ/k5L7BUaaZcoz5VAAxrkeMjGSolFR7ndhb4laPm 3U2q/+8M= X-Gm-Gg: ASbGncvx7qO4KxtIpHotPjjs3W/VdbIonK5W9x5BHpd1zPvVtx3jiTDSrA28Y2zJmNp f/lLXQDD4AYCKufi+99Jweda7lfB7z5C4xkBfF8HejzuT3Oqi/iGkHJ9lqf0fz3n7lqMyfINDKJ JYmxXw1fblXni80I6heTf+j5Qz32eh57etJ4i5HSZA0XoopOE5trQVFX2AgcDi+y18sLNhEF41k QIAtE4qPxSa/NowXTLt8Cp2YJXhgQrns7zTITMXnOXZQiYl3AzD1Olh/S7bdLOx62i4w87siYjD /laGWFg2wl3TEx7waOxTEfvbZxLrMZgCT41X/UAmydtXC+qZRgP+kQqDVWQh3f84/kT77/t7wCF NAMa7/XkEO6XT2S/SvbiV6cB0O58HxjbZ1QF3ZhnDjAYPq33ElCrJMpO2EnPtV8iL2i+2Ee6Kii X0lfhN0FU9Xi5lZlgmMb5OfLQpJaabHRM3jlGU6zss X-Google-Smtp-Source: AGHT+IGKiCuM5ESjgUwH6uI2oOkhTG4j1HcCwu++mPHCcFMMr6r+8s0GUNV45rmPuEx4piBUnxA7VQ== X-Received: by 2002:a17:907:6088:b0:b4c:629b:aa67 with SMTP id a640c23a62f3a-b70522030bfmr679282466b.32.1761911617139; Fri, 31 Oct 2025 04:53:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , Manos Pitsidianakis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 1/5] accel/tcg: Introduce and use MO_ALIGN_TLB_ONLY Date: Fri, 31 Oct 2025 12:53:29 +0100 Message-ID: <20251031115334.368165-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251031115334.368165-1-richard.henderson@linaro.org> References: <20251031115334.368165-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761911722473158500 For Arm, we need 3 cases: (1) the alignment required when accessing Normal memory, (2) the alignment required when accessing Device memory, and (3) the atomicity of the access. When we added TLB_CHECK_ALIGNED, we assumed that cases 2 and 3 were identical, and thus used memop_atomicity_bits for TLB_CHECK_ALIGNED. This is incorrect for multiple reasons, including that the atomicity of the access is adjusted depending on whether or not we are executing within a serial context. For Arm, what is true is that there is an underlying alignment requirement of the access, and for that access Normal memory will support unalignement. Introduce MO_ALIGN_TLB_ONLY to indicate that the alignment specified in MO_AMASK only applies when the TLB entry has TLB_CHECK_ALIGNED set; otherwise no alignment required. Introduce memop_tlb_alignment_bits with an additional bool argument that specifies whether TLB_CHECK_ALIGNED is set. All other usage of memop_alignment_bits assumes it is not. Remove memop_atomicity_bits as unused; it didn't properly support MO_ATOM_SUBWORD anyway. Update target/arm finalize_memop_atom to set MO_ALIGN_TLB_ONLY when strict alignment isn't otherwise required. Suggested-by: Peter Maydell Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3171 Signed-off-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/memop.h | 43 +++++++++++++++------------------ target/arm/tcg/translate.h | 4 +-- accel/tcg/cputlb.c | 13 +--------- target/arm/ptw.c | 2 +- target/arm/tcg/translate-a64.c | 10 +++----- target/arm/tcg/translate-neon.c | 2 +- tcg/tcg.c | 10 +++++--- 7 files changed, 35 insertions(+), 49 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index cf7da3362e..799b5b4221 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -72,6 +72,16 @@ typedef enum MemOp { MO_ALIGN_64 =3D 6 << MO_ASHIFT, MO_ALIGN =3D MO_AMASK, =20 + /* + * MO_ALIGN_TLB_ONLY: + * Apply MO_AMASK only along the TCG slow path if TLB_CHECK_ALIGNED + * is set; otherwise unaligned access is permitted. + * This is used by target/arm, where unaligned accesses are + * permitted for pages marked Normal but aligned accesses are + * required for pages marked Device. + */ + MO_ALIGN_TLB_ONLY =3D 1 << 8, + /* * MO_ATOM_* describes the atomicity requirements of the operation: * MO_ATOM_IFALIGN: the operation must be single-copy atomic if it @@ -104,7 +114,7 @@ typedef enum MemOp { * size of the operation, if aligned. This retains the behaviour * from before this field was introduced. */ - MO_ATOM_SHIFT =3D 8, + MO_ATOM_SHIFT =3D 9, MO_ATOM_IFALIGN =3D 0 << MO_ATOM_SHIFT, MO_ATOM_IFALIGN_PAIR =3D 1 << MO_ATOM_SHIFT, MO_ATOM_WITHIN16 =3D 2 << MO_ATOM_SHIFT, @@ -169,16 +179,16 @@ static inline MemOp size_memop(unsigned size) } =20 /** - * memop_alignment_bits: + * memop_tlb_alignment_bits: * @memop: MemOp value * - * Extract the alignment size from the memop. + * Extract the alignment size for use with TLB_CHECK_ALIGNED. */ -static inline unsigned memop_alignment_bits(MemOp memop) +static inline unsigned memop_tlb_alignment_bits(MemOp memop, bool tlb_chec= k) { unsigned a =3D memop & MO_AMASK; =20 - if (a =3D=3D MO_UNALN) { + if (a =3D=3D MO_UNALN || (!tlb_check && (memop & MO_ALIGN_TLB_ONLY))) { /* No alignment required. */ a =3D 0; } else if (a =3D=3D MO_ALIGN) { @@ -191,28 +201,15 @@ static inline unsigned memop_alignment_bits(MemOp mem= op) return a; } =20 -/* - * memop_atomicity_bits: +/** + * memop_alignment_bits: * @memop: MemOp value * - * Extract the atomicity size from the memop. + * Extract the alignment size from the memop. */ -static inline unsigned memop_atomicity_bits(MemOp memop) +static inline unsigned memop_alignment_bits(MemOp memop) { - unsigned size =3D memop & MO_SIZE; - - switch (memop & MO_ATOM_MASK) { - case MO_ATOM_NONE: - size =3D MO_8; - break; - case MO_ATOM_IFALIGN_PAIR: - case MO_ATOM_WITHIN16_PAIR: - size =3D size ? size - 1 : 0; - break; - default: - break; - } - return size; + return memop_tlb_alignment_bits(memop, false); } =20 #endif diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 9a85ea74db..b62104b4ae 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -744,8 +744,8 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour = flavour) */ static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp = atom) { - if (s->align_mem && !(opc & MO_AMASK)) { - opc |=3D MO_ALIGN; + if (!(opc & MO_AMASK)) { + opc |=3D MO_ALIGN | (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); } return opc | atom | s->be_data; } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 631f1fe135..fd1606c856 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1668,18 +1668,7 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPage= Data *data, MemOp memop, =20 if (likely(!maybe_resized)) { /* Alignment has not been checked by tlb_fill_align. */ - int a_bits =3D memop_alignment_bits(memop); - - /* - * This alignment check differs from the one above, in that this is - * based on the atomicity of the operation. The intended use case = is - * the ARM memory type field of each PTE, where access to pages wi= th - * Device memory type require alignment. - */ - if (unlikely(flags & TLB_CHECK_ALIGNED)) { - int at_bits =3D memop_atomicity_bits(memop); - a_bits =3D MAX(a_bits, at_bits); - } + int a_bits =3D memop_tlb_alignment_bits(memop, flags & TLB_CHECK_A= LIGNED); if (unlikely(addr & ((1 << a_bits) - 1))) { cpu_unaligned_access(cpu, addr, access_type, mmu_idx, ra); } diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 23f6616811..2e6b149b2d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2352,7 +2352,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) */ if (device) { - unsigned a_bits =3D memop_atomicity_bits(memop); + unsigned a_bits =3D memop_tlb_alignment_bits(memop, true); if (address & ((1 << a_bits) - 1)) { fi->type =3D ARMFault_Alignment; goto do_fault; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3292d7cbfd..08b21d7dbf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3691,9 +3691,8 @@ static bool trans_STP(DisasContext *s, arg_ldstpair *= a) * In all cases, issue one operation with the correct atomicity. */ mop =3D a->sz + 1; - if (s->align_mem) { - mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); - } + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + mop |=3D (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); mop =3D finalize_memop_pair(s, mop); if (a->sz =3D=3D 2) { TCGv_i64 tmp =3D tcg_temp_new_i64(); @@ -3742,9 +3741,8 @@ static bool trans_LDP(DisasContext *s, arg_ldstpair *= a) * since that reuses the most code below. */ mop =3D a->sz + 1; - if (s->align_mem) { - mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); - } + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + mop |=3D (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); mop =3D finalize_memop_pair(s, mop); if (a->sz =3D=3D 2) { int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 844d2e29e4..e3c7d9217b 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -520,7 +520,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) if (a->align) { align =3D pow2_align(a->align + 2); /* 4 ** a->align */ } else { - align =3D s->align_mem ? MO_ALIGN : 0; + align =3D MO_ALIGN | (s->align_mem ? 0 : MO_ALIGN_TLB_ONLY); } =20 /* diff --git a/tcg/tcg.c b/tcg/tcg.c index 294762c283..fbf09f5c82 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3039,20 +3039,22 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have= _prefs) case INDEX_op_qemu_ld2: case INDEX_op_qemu_st2: { - const char *s_al, *s_op, *s_at; + const char *s_al, *s_tlb, *s_op, *s_at; MemOpIdx oi =3D op->args[k++]; MemOp mop =3D get_memop(oi); unsigned ix =3D get_mmuidx(oi); =20 + s_tlb =3D mop & MO_ALIGN_TLB_ONLY ? "tlb+" : ""; s_al =3D alignment_name[(mop & MO_AMASK) >> MO_ASHIFT]; s_op =3D ldst_name[mop & (MO_BSWAP | MO_SSIZE)]; s_at =3D atom_name[(mop & MO_ATOM_MASK) >> MO_ATOM_SHI= FT]; - mop &=3D ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MA= SK); + mop &=3D ~(MO_AMASK | MO_BSWAP | MO_SSIZE | + MO_ATOM_MASK | MO_ALIGN_TLB_ONLY); =20 /* If all fields are accounted for, print symbolically= . */ if (!mop && s_al && s_op && s_at) { - col +=3D ne_fprintf(f, ",%s%s%s,%u", - s_at, s_al, s_op, ix); + col +=3D ne_fprintf(f, ",%s%s%s%s,%u", + s_at, s_al, s_tlb, s_op, ix); } else { mop =3D get_memop(oi); col +=3D ne_fprintf(f, ",$0x%x,%u", mop, ix); --=20 2.43.0 From nobody Fri Nov 14 16:40:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761911713; cv=none; d=zohomail.com; s=zohoarc; b=Y0Q1ZizJHY1u1X2QgtEHRtTn80b85Wof/LzKmc+6oheuOzd1NTnYOmHIUSeVNWJv32ovzYic7045qfIiok1XtFdA/lFrCAiQbLSTzuOt9uCi6zMwM3dYhuc11U7PCzBt5S6Pky9PsxI3WAUEUaJqxHZXBRt6Frm7ti7yE1TW66s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761911713; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1JOuSiiYqzLFJt0ZlK3iLHRsXfFv3l4QDbV0ydr0oXM=; b=KdxUSEYWJyqPiSFPhtv3+tanaVi/jnbxUeJrkrtjToS4PxATMVwBENzhe4pjAj7jLRZJqSAgnjVpql/f1EwW9xog2L/xatjp4DLrHd6cTXBWso0MfbksG0lFuBk/kU2nrRo8pzX8FCGYz6W9rbEUJZ34gioxQeot+5MzAkBuoBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761911713671377.2470200172593; Fri, 31 Oct 2025 04:55:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vEnho-0007Zp-8d; Fri, 31 Oct 2025 07:54:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vEnhi-0007XO-Kb for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:54:03 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vEnhX-0005xW-Aq for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:54:02 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-b3d196b7eeeso460105266b.0 for ; Fri, 31 Oct 2025 04:53:44 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index dfa5c38728..ab7b409be6 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1818,30 +1818,16 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,= TCGv_i64 arg1, tcg_gen_movi_i32(TCGV_LOW(ret), 0); } } else if (right) { - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - tcg_gen_extract2_i32(TCGV_LOW(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), c); - } else { - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret), - TCGV_HIGH(arg1), 32 - c, c); - } + tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), c); if (arith) { tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); } else { tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); } } else { - if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { - tcg_gen_extract2_i32(TCGV_HIGH(ret), - TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c); - tcg_gen_deposit_i32(TCGV_HIGH(ret), t0, - TCGV_HIGH(arg1), c, 32 - c); - tcg_temp_free_i32(t0); - } + tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), + TCGV_HIGH(arg1), 32 - c); tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); } } --=20 2.43.0 From nobody Fri Nov 14 16:40:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761911749; cv=none; d=zohomail.com; s=zohoarc; b=klrjxu0QDb4UUonelow3a9Y+c4/BIVppwWj1rK4QL1c4DNRSrMg+aKs2swzKCpnaV8exxQ8npcAVtMuiRhefT0VnlkA4XNkRdc+9aEHe6anSiNrYnzxQPdfxjUsNryLMWKN82hUrtHdJAyXHASvFcT6unSr2c44ZxEjcnri6oe4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761911749; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=brUq3/ArxO91G6+DeWcEGxfRqjtJMC2k/usTFUU+3E0=; b=KINSGpUVYZdNGHAIwbNkYvE5QB+WWwgAebMRW9ZV8FsRlaLzFTD749wFaEm2i5kOkp14xT+Mvig6rnS0pnuegFI9B7Q4EvLTfaFJLCrif2sDaYC8LdXA52RHHtxSxMH/ZKaJEQHHulpq5R5uWw9CfM4b+SsSi50agYCRckhuZxk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761911749903837.8384905562898; Fri, 31 Oct 2025 04:55:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vEnhh-0007WV-0e; Fri, 31 Oct 2025 07:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vEnhd-0007Uv-2r for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:53:57 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vEnhS-0005xZ-Rs for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:53:56 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-b4736e043f9so369153266b.0 for ; Fri, 31 Oct 2025 04:53:43 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20251031094118.28440-2-philmd@linaro.org> --- tests/functional/mips/test_replay.py | 2 ++ tests/functional/mips64el/test_replay.py | 2 ++ 2 files changed, 4 insertions(+) diff --git a/tests/functional/mips/test_replay.py b/tests/functional/mips/t= est_replay.py index 4327481e35..747835bf00 100755 --- a/tests/functional/mips/test_replay.py +++ b/tests/functional/mips/test_replay.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 from qemu_test import Asset, skipSlowTest +from qemu_test import skipFlakyTest from replay_kernel import ReplayKernelBase =20 =20 @@ -16,6 +17,7 @@ class MipsReplay(ReplayKernelBase): 'linux-image-2.6.32-5-4kc-malta_2.6.32-48_mips.deb'), '16ca524148afb0626f483163e5edf352bc1ab0e4fc7b9f9d473252762f2c7a43') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/2013") def test_replay_mips_malta(self): self.set_machine('malta') kernel_path =3D self.archive_extract(self.ASSET_KERNEL_2_63_2, diff --git a/tests/functional/mips64el/test_replay.py b/tests/functional/mi= ps64el/test_replay.py index 26a6ccff3f..05cc585f85 100755 --- a/tests/functional/mips64el/test_replay.py +++ b/tests/functional/mips64el/test_replay.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 from qemu_test import Asset, skipUntrustedTest +from qemu_test import skipFlakyTest from replay_kernel import ReplayKernelBase =20 =20 @@ -16,6 +17,7 @@ class Mips64elReplay(ReplayKernelBase): 'linux-image-2.6.32-5-5kc-malta_2.6.32-48_mipsel.deb'), '35eb476f03be589824b0310358f1c447d85e645b88cbcd2ac02b97ef560f9f8d') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/2013") def test_replay_mips64el_malta(self): self.set_machine('malta') kernel_path =3D self.archive_extract(self.ASSET_KERNEL_2_63_2, --=20 2.43.0 From nobody Fri Nov 14 16:40:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761911766; cv=none; d=zohomail.com; s=zohoarc; b=K2z8qNTIpXZy9aA+Jf6O9RFmT2IDmDU8B3jQ+nuNE8/C7/QtjP7u+Ul71U74WFBtxcuhgiGs2h+LIxrV7yZulabYIjSyNJyW/QuFZiBqrdIEkuyoAXlbCabl0xzlzlqMBfbYfi18Rx1x6KJT9FixKCPjAAXVwuK0e1EEISmGsmo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761911766; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2I/yueIXmHU+++rshocZvOrvBhzR3OdLvTc+kjqGUpk=; b=MVl4eLplODviG4H8VpZ+Rn/B/Pv7BCKwbQ4Fy1irgJJNS6WQhTsX1im3ipgVuotD5MMH5kq6oI/vN5wH2kWl+rDw9/V48kFh8gfNTMnEciqkU4B5g3j8R5RyJChP1jEOtln1goGERhAmdKyT1JsUC9uOk+yfl2ycD7VTOySPaOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761911766958974.0209932251087; Fri, 31 Oct 2025 04:56:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vEnhj-0007Xt-7S; Fri, 31 Oct 2025 07:54:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vEnhg-0007Wl-7l for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:54:01 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vEnhS-0005xi-He for qemu-devel@nongnu.org; Fri, 31 Oct 2025 07:53:59 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-b6d6984a5baso412688666b.3 for ; Fri, 31 Oct 2025 04:53:44 -0700 (PDT) Received: from stoup.. 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[modprobe:208] 07:17,707: Modules linked in: 07:17,707: Cpu 0 07:17,708: $ 0 : 00000000 1000a400 0000003d 87808b00 07:17,708: $ 4 : 87808b00 87808bf0 00000000 00000000 07:17,709: $ 8 : 86862100 86862100 86862100 86862100 07:17,709: $12 : 86862100 00000000 00000001 86862100 07:17,709: $16 : 87808a00 86862100 1000a401 c008fa60 07:17,709: $20 : 86862100 8041d230 00000000 ffff0000 07:17,710: $24 : 00000000 77711470 07:17,710: $28 : 87bb6000 87bb7df8 8041d230 801f7388 07:17,710: Hi : 00000000 07:17,710: Lo : 00000000 07:17,711: epc : 801f7308 kfree+0x104/0x19c 07:17,711: Not tainted 07:17,711: ra : 801f7388 kfree+0x184/0x19c 07:17,712: Status: 1000a403 KERNEL EXL IE 07:17,712: Cause : 50808000 07:17,712: PrId : 00019300 (MIPS 24Kc) 07:45,707: BUG: soft lockup - CPU#0 stuck for 22s! [modprobe:208] 07:45,707: Modules linked in: Reported-by: Daniel P. Berrang=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20251031094118.28440-3-philmd@linaro.org> --- tests/functional/mips/test_malta.py | 2 ++ tests/functional/mips64/test_malta.py | 2 ++ tests/functional/mips64el/test_malta.py | 1 + tests/functional/mipsel/test_malta.py | 2 ++ 4 files changed, 7 insertions(+) diff --git a/tests/functional/mips/test_malta.py b/tests/functional/mips/te= st_malta.py index 30279f0ff2..7a734bc069 100755 --- a/tests/functional/mips/test_malta.py +++ b/tests/functional/mips/test_malta.py @@ -9,6 +9,7 @@ import os =20 from qemu_test import LinuxKernelTest, Asset, wait_for_console_pattern +from qemu_test import skipFlakyTest from qemu_test import exec_command_and_wait_for_pattern =20 =20 @@ -181,6 +182,7 @@ def test_mips_malta_cpio(self): 'debian_wheezy_mips_standard.qcow2'), 'de03599285b8382ad309309a6c4869f6c6c42a5cfc983342bab9ec0dfa7849a2') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/3109") def test_wheezy(self): kernel_path =3D self.ASSET_WHEEZY_KERNEL.fetch() image_path =3D self.ASSET_WHEEZY_DISK.fetch() diff --git a/tests/functional/mips64/test_malta.py b/tests/functional/mips6= 4/test_malta.py index a553d3c5bc..91c57c56af 100755 --- a/tests/functional/mips64/test_malta.py +++ b/tests/functional/mips64/test_malta.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 from qemu_test import LinuxKernelTest, Asset +from qemu_test import skipFlakyTest from mips.test_malta import mips_check_wheezy =20 =20 @@ -20,6 +21,7 @@ class MaltaMachineConsole(LinuxKernelTest): 'debian_wheezy_mips_standard.qcow2'), 'de03599285b8382ad309309a6c4869f6c6c42a5cfc983342bab9ec0dfa7849a2') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/3109") def test_wheezy(self): kernel_path =3D self.ASSET_WHEEZY_KERNEL.fetch() image_path =3D self.ASSET_WHEEZY_DISK.fetch() diff --git a/tests/functional/mips64el/test_malta.py b/tests/functional/mip= s64el/test_malta.py index 170147bfcc..e37463dc29 100755 --- a/tests/functional/mips64el/test_malta.py +++ b/tests/functional/mips64el/test_malta.py @@ -102,6 +102,7 @@ def test_mips64el_malta_5KEc_cpio(self): 'debian_wheezy_mipsel_standard.qcow2'), '454f09ae39f7e6461c84727b927100d2c7813841f2a0a5dce328114887ecf914') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/3109") def test_wheezy(self): kernel_path =3D self.ASSET_WHEEZY_KERNEL.fetch() image_path =3D self.ASSET_WHEEZY_DISK.fetch() diff --git a/tests/functional/mipsel/test_malta.py b/tests/functional/mipse= l/test_malta.py index 427e163d19..59ab4a6058 100755 --- a/tests/functional/mipsel/test_malta.py +++ b/tests/functional/mipsel/test_malta.py @@ -10,6 +10,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later =20 from qemu_test import QemuSystemTest, LinuxKernelTest, Asset +from qemu_test import skipFlakyTest from qemu_test import interrupt_interactive_console_until_pattern from qemu_test import wait_for_console_pattern =20 @@ -69,6 +70,7 @@ def test_mips_malta32el_nanomips_64k_dbg(self): 'debian_wheezy_mipsel_standard.qcow2'), '454f09ae39f7e6461c84727b927100d2c7813841f2a0a5dce328114887ecf914') =20 + @skipFlakyTest("https://gitlab.com/qemu-project/qemu/-/issues/3109") def test_wheezy(self): kernel_path =3D self.ASSET_WHEEZY_KERNEL.fetch() image_path =3D self.ASSET_WHEEZY_DISK.fetch() --=20 2.43.0 From nobody Fri Nov 14 16:40:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Instead we skip the copying of the user data and possible processing through fd_trans_target_to_host_data, and call the host syscall with NULL, 0. (unlock_user() permits a NULL buffer pointer for "do nothing" so we don't need to special case the unlock code.) Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3102 Signed-off-by: Peter Maydell Reviewed-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20251028142001.3011630-1-peter.maydell@linaro.org> --- linux-user/syscall.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 8546f48a05..2060e561a2 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3581,7 +3581,7 @@ static abi_long do_sendto(int fd, abi_ulong msg, size= _t len, int flags, abi_ulong target_addr, socklen_t addrlen) { void *addr; - void *host_msg; + void *host_msg =3D NULL; void *copy_msg =3D NULL; abi_long ret; =20 @@ -3589,16 +3589,19 @@ static abi_long do_sendto(int fd, abi_ulong msg, si= ze_t len, int flags, return -TARGET_EINVAL; } =20 - host_msg =3D lock_user(VERIFY_READ, msg, len, 1); - if (!host_msg) - return -TARGET_EFAULT; - if (fd_trans_target_to_host_data(fd)) { - copy_msg =3D host_msg; - host_msg =3D g_malloc(len); - memcpy(host_msg, copy_msg, len); - ret =3D fd_trans_target_to_host_data(fd)(host_msg, len); - if (ret < 0) { - goto fail; + if (len !=3D 0) { + host_msg =3D lock_user(VERIFY_READ, msg, len, 1); + if (!host_msg) { + return -TARGET_EFAULT; + } + if (fd_trans_target_to_host_data(fd)) { + copy_msg =3D host_msg; + host_msg =3D g_malloc(len); + memcpy(host_msg, copy_msg, len); + ret =3D fd_trans_target_to_host_data(fd)(host_msg, len); + if (ret < 0) { + goto fail; + } } } if (target_addr) { --=20 2.43.0