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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 10:52:53.2271 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61d07813-6efd-438c-a407-08de186ba480 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7571 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=skolothumtho@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1761908072881158500 Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need different callback handling in upcoming patches. This also adds a CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled at compile time. Because we now include CONFIG_DEVICES in the header to check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to be changed to arm_ss.add. The =E2=80=9Caccel=E2=80=9D property isn=E2=80=99t user visible yet and it = will be introduced in a later patch once all the supporting pieces are ready. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 3 ++- hw/arm/smmuv3-accel.c | 59 +++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 27 +++++++++++++++++++ hw/arm/smmuv3.c | 5 ++++ include/hw/arm/smmuv3.h | 3 +++ 6 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 hw/arm/smmuv3-accel.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b44b85f436..3a6dc122ef 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -12,6 +12,7 @@ config ARM_VIRT select ARM_GIC select ACPI select ARM_SMMUV3 + select ARM_SMMUV3_ACCEL select GPIO_KEY select DEVICE_TREE select FW_CFG_DMA @@ -628,6 +629,10 @@ config FSL_IMX8MP_EVK config ARM_SMMUV3 bool =20 +config ARM_SMMUV3_ACCEL + bool + depends on ARM_SMMUV3 && IOMMUFD + config FSL_IMX6UL bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b88b5b06d7..32ec214434 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -62,7 +62,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..99ef0db8c4 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" + +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + return container_of(sdev, SMMUv3AccelDevice, sdev); + } + + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(bs, sdev, bus, devfn); + return accel_dev; +} + +/* + * Find or add an address space for the given PCI device. + * + * If a device matching @bus and @devfn already exists, return its + * corresponding address space. Otherwise, create a new device entry + * and initialize address space for it. + */ +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + +static const PCIIOMMUOps smmuv3_accel_ops =3D { + .get_address_space =3D smmuv3_accel_find_add_as, +}; + +void smmuv3_accel_init(SMMUv3State *s) +{ + SMMUState *bs =3D ARM_SMMU(s); + + bs->iommu_ops =3D &smmuv3_accel_ops; +} diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..0dc6b00d35 --- /dev/null +++ b/hw/arm/smmuv3-accel.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include CONFIG_DEVICES + +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + +#ifdef CONFIG_ARM_SMMUV3_ACCEL +void smmuv3_accel_init(SMMUv3State *s); +#else +static inline void smmuv3_accel_init(SMMUv3State *s) +{ +} +#endif + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bcf8af8dc7..ef991cb7d8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ #include "qapi/error.h" =20 #include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" #include "smmuv3-internal.h" #include "smmu-internal.h" =20 @@ -1882,6 +1883,10 @@ static void smmu_realize(DeviceState *d, Error **err= p) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + if (s->accel) { + smmuv3_accel_init(s); + } + c->parent_realize(d, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..bb7076286b 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,9 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + + /* SMMU has HW accelerator support for nested S1 + s2 */ + bool accel; }; =20 typedef enum { --=20 2.43.0