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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v5 31/32] vfio: Synthesize vPASID capability to VM Date: Fri, 31 Oct 2025 10:50:04 +0000 Message-ID: <20251031105005.24618-32-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251031105005.24618-1-skolothumtho@nvidia.com> References: <20251031105005.24618-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FD:EE_|PH7PR12MB5806:EE_ X-MS-Office365-Filtering-Correlation-Id: 15dd7500-2a5b-4f82-11b1-08de186bf67a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" From: Yi Liu If user wants to expose PASID capability in vIOMMU, then VFIO would also report the PASID cap for this device if the underlying hardware supports it as well. As a start, this chooses to put the vPASID cap in the last 8 bytes of the vconfig space. This is a choice in the good hope of no conflict with any existing cap or hidden registers. For the devices that has hidden registers, user should figure out a proper offset for the vPASID cap. This may require an option for user to config it. Here we leave it as a future extension. There are more discussions on the mechanism of finding the proper offset. https://lore.kernel.org/kvm/BN9PR11MB5276318969A212AD0649C7BE8CBE2@BN9PR11M= B5276.namprd11.prod.outlook.com/ Since we add a check to ensure the vIOMMU supports PASID, only devices under those vIOMMUs can synthesize the vPASID capability. This gives users control over which devices expose vPASID. Signed-off-by: Yi Liu Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron --- hw/vfio/pci.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/iommu.h | 1 + 2 files changed, 38 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 06b06afc2b..2054eac897 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -24,6 +24,7 @@ #include =20 #include "hw/hw.h" +#include "hw/iommu.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci_bridge.h" @@ -2500,7 +2501,12 @@ static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev= , uint16_t pos) =20 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) { + HostIOMMUDevice *hiod =3D vdev->vbasedev.hiod; + HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); PCIDevice *pdev =3D PCI_DEVICE(vdev); + uint64_t max_pasid_log2 =3D 0; + bool pasid_cap_added =3D false; + uint64_t hw_caps; uint32_t header; uint16_t cap_id, next, size; uint8_t cap_ver; @@ -2578,12 +2584,43 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) pcie_add_capability(pdev, cap_id, cap_ver, next, size); } break; + case PCI_EXT_CAP_ID_PASID: + pasid_cap_added =3D true; + /* fallthrough */ default: pcie_add_capability(pdev, cap_id, cap_ver, next, size); } =20 } =20 +#ifdef CONFIG_IOMMUFD + /* + * Although we check for PCI_EXT_CAP_ID_PASID above, the Linux VFIO + * framework currently hides this capability. Try to retrieve it + * through alternative kernel interfaces (e.g. IOMMUFD APIs). + */ + if (!pasid_cap_added && hiodc->get_cap) { + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_GENERIC_HW, &hw_caps, N= ULL); + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_MAX_PASID_LOG2, + &max_pasid_log2, NULL); + } + + /* + * If supported, adds the PASID capability in the end of the PCIe conf= ig + * space. TODO: Add option for enabling pasid at a safe offset. + */ + if (max_pasid_log2 && (pci_device_get_viommu_flags(pdev) & + VIOMMU_FLAG_PASID_SUPPORTED)) { + bool exec_perm =3D (hw_caps & IOMMU_HW_CAP_PCI_PASID_EXEC) ? true = : false; + bool priv_mod =3D (hw_caps & IOMMU_HW_CAP_PCI_PASID_PRIV) ? true := false; + + pcie_pasid_init(pdev, PCIE_CONFIG_SPACE_SIZE - PCI_EXT_CAP_PASID_S= IZEOF, + max_pasid_log2, exec_perm, priv_mod); + /* PASID capability is fully emulated by QEMU */ + memset(vdev->emulated_config_bits + pdev->exp.pasid_cap, 0xff, 8); + } +#endif + /* Cleanup chain head ID if necessary */ if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) =3D=3D 0xFFFF) { pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); diff --git a/include/hw/iommu.h b/include/hw/iommu.h index 9b8bb94fc2..9635770bee 100644 --- a/include/hw/iommu.h +++ b/include/hw/iommu.h @@ -20,6 +20,7 @@ enum viommu_flags { /* vIOMMU needs nesting parent HWPT to create nested HWPT */ VIOMMU_FLAG_WANT_NESTING_PARENT =3D BIT_ULL(0), + VIOMMU_FLAG_PASID_SUPPORTED =3D BIT_ULL(1), }; =20 #endif /* HW_IOMMU_H */ --=20 2.43.0