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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 10:54:42.8510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1859523-4165-453e-618d-08de186be5de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6522 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=skolothumtho@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1761908715347154100 Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode is enabled, RIL has=C2=A0to be compatible with host SMMUv3 support. Add a property so that the user can specify this. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/smmuv3-accel.c | 15 +++++++++++++-- hw/arm/smmuv3-accel.h | 4 ++++ hw/arm/smmuv3.c | 12 ++++++++++++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 8b9f88dd8e..35298350cb 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -63,10 +63,10 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 - /* QEMU SMMUv3 supports Range Invalidation by default */ + /* User can disable QEMU SMMUv3 Range Invalidation support */ if (FIELD_EX32(info->idr[3], IDR3, RIL) !=3D FIELD_EX32(s->idr[3], IDR3, RIL)) { - error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); + error_setg(errp, "Host SMMUv3 differs in Range Invalidation suppor= t"); return false; } =20 @@ -635,6 +635,17 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_address_space =3D smmuv3_accel_get_msi_as, }; =20 +void smmuv3_accel_idr_override(SMMUv3State *s) +{ + if (!s->accel) { + return; + } + + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ + if (!s->ril) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } +} =20 /* Based on SMUUv3 GBPA configuration, attach a corresponding HWPT */ void smmuv3_accel_gbpa_update(SMMUv3State *s) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index ee79548370..4f5b672712 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -55,6 +55,7 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, Error **errp); void smmuv3_accel_gbpa_update(SMMUv3State *s); void smmuv3_accel_reset(SMMUv3State *s); +void smmuv3_accel_idr_override(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -83,6 +84,9 @@ static inline void smmuv3_accel_gbpa_update(SMMUv3State *= s) static inline void smmuv3_accel_reset(SMMUv3State *s) { } +static inline void smmuv3_accel_idr_override(SMMUv3State *s) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index f040e6b91e..b9d96f5762 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -305,6 +305,7 @@ static void smmuv3_init_id_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); s->aidr =3D 0x1; + smmuv3_accel_idr_override(s); } =20 static void smmuv3_reset(SMMUv3State *s) @@ -1936,6 +1937,13 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } #endif + if (!s->accel) { + if (!s->ril) { + error_setg(errp, "ril can only be disabled if accel=3Don"); + return false; + } + return false; + } return true; } =20 @@ -2057,6 +2065,8 @@ static const Property smmuv3_properties[] =3D { */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), + /* RIL can be turned off for accel cases */ + DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2084,6 +2094,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator suppo= rt." "Allows host SMMUv3 to be config= ured " "in nested mode for vfio-pci dev= assignment"); + object_class_property_set_description(klass, "ril", + "Disable range invalidation support (for accel=3Don)"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6b9c27a9c4..95202c2757 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -68,6 +68,7 @@ struct SMMUv3State { bool accel; struct SMMUv3AccelState *s_accel; Error *migration_blocker; + bool ril; }; =20 typedef enum { --=20 2.43.0