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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 10:54:04.0221 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dac1f42e-ab1c-4f54-13fd-08de186bceb8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9024 Received-SPF: permerror client-ip=2a01:111:f403:c001::2; envelope-from=skolothumtho@nvidia.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1761908160760154101 Provide a helper and use that to issue the invalidation cmd to host SMMUv3. We only issue one cmd at a time for now. Support for batching of commands=C2=A0will be added later after analysing t= he impact. Reviewed-by: Jonathan Cameron Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- hw/arm/smmuv3-accel.c | 35 +++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 8 ++++++++ hw/arm/smmuv3.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 395c8175da..a2deda3c32 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -213,6 +213,41 @@ bool smmuv3_accel_install_nested_ste_range(SMMUv3State= *s, SMMUSIDRange *range, return true; } =20 +/* + * This issues the invalidation cmd to the host SMMUv3. + * Note: sdev can be NULL for certain invalidation commands + * e.g., SMMU_CMD_TLBI_NH_ASID, SMMU_CMD_TLBI_NH_VA etc. + */ +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sd= ev, + Error **errp) +{ + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + IOMMUFDViommu *viommu; + uint32_t entry_num =3D 1; + + /* No vIOMMU means no VFIO/IOMMUFD devices, nothing to invalidate. */ + if (!s_accel || !s_accel->vsmmu) { + return true; + } + + /* + * Called for emulated bridges or root ports, but SID-based + * invalidations (e.g. CFGI_CD) apply only to vfio-pci endpoints + * with a valid vIOMMU vdev. + */ + if (sdev && !container_of(sdev, SMMUv3AccelDevice, sdev)->vdev) { + return true; + } + + viommu =3D &s_accel->vsmmu->viommu; + /* Single command (entry_num =3D 1); no need to check returned entry_n= um */ + return iommufd_backend_invalidate_cache( + viommu->iommufd, viommu->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3, + sizeof(Cmd), &entry_num, cmd, errp); +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 8931e83dc5..ee79548370 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -51,6 +51,8 @@ bool smmuv3_accel_install_nested_ste(SMMUv3State *s, SMMU= Device *sdev, int sid, Error **errp); bool smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SMMUSIDRange *r= ange, Error **errp); +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, + Error **errp); void smmuv3_accel_gbpa_update(SMMUv3State *s); void smmuv3_accel_reset(SMMUv3State *s); #else @@ -69,6 +71,12 @@ smmuv3_accel_install_nested_ste_range(SMMUv3State *s, SM= MUSIDRange *range, { return true; } +static inline bool +smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, + Error **errp) +{ + return true; +} static inline void smmuv3_accel_gbpa_update(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cc32b618ed..15173ddc9c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1381,6 +1381,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint32_t sid =3D CMD_SID(&cmd); SMMUDevice *sdev =3D smmu_find_sdev(bs, sid); + Error *local_err =3D NULL; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; @@ -1393,11 +1394,17 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_cd(sid); smmuv3_flush_config(sdev); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ASID: { int asid =3D CMD_ASID(&cmd); + Error *local_err =3D NULL; int vmid =3D -1; =20 if (!STAGE1_SUPPORTED(s)) { @@ -1416,6 +1423,11 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; } case SMMU_CMD_TLBI_NH_ALL: @@ -1440,18 +1452,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) QEMU_FALLTHROUGH; } case SMMU_CMD_TLBI_NSNH_ALL: + { + Error *local_err =3D NULL; + trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; + } case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: + { + Error *local_err =3D NULL; + if (!STAGE1_SUPPORTED(s)) { cmd_error =3D SMMU_CERROR_ILL; break; } smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, &local_err)) { + error_report_err(local_err); + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; + } case SMMU_CMD_TLBI_S12_VMALL: { int vmid =3D CMD_VMID(&cmd); --=20 2.43.0