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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761843578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=FQqSwxzlY/jt/p8yntQFpycFXxTFVhchNKEJY6m+p5c=; b=M/jYCD/LQDrcGqFfr4WHKG90v4yENMFbhcg7CoVbALR3lTh7alhcw3UfjnkLHAKMx0kzQ6 RRqPMjAmvUaaaU3n+5oHg5CNrwE7VtV0zlQrh5WKAwN4XI1uMe1w6tsq1Rt9wbUSBHfvfG QY1yMtmIHP44JiE8Na42gOXl0ESxOMA= X-MC-Unique: W7btx3zsNuqqNCytLytaBA-1 X-Mimecast-MFC-AGG-ID: W7btx3zsNuqqNCytLytaBA_1761843575 From: Igor Mammedov To: qemu-devel@nongnu.org Cc: yoshinori.sato@nifty.com, Thomas Huth Subject: [PATCH] rx: cpu: fix interrupts check in rx_cpu_do_interrupt() Date: Thu, 30 Oct 2025 17:59:32 +0100 Message-ID: <20251030165932.138512-1-imammedo@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761843702938154100 Commit [1] broke interrupt handling, replacing interrupts fetch with a bool and then the remaining code attempting to check individual bits on that bool value, which effectively masked those interrupts. Fix it by checking individual interrupt bits directly instead of old 'fetch then check' approach. 1) Fixes: 87511341c30d ("add cpu_test_interrupt()/cpu_set_interrupt() helpers = and use them tree wide") Reported-by: Thomas Huth Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Tested-by: Thomas Huth --- target/rx/helper.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/target/rx/helper.c b/target/rx/helper.c index 41c9606fd1..19af212b7d 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -40,11 +40,9 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, in= t rte) env->psw_c =3D FIELD_EX32(psw, PSW, C); } =20 -#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { CPURXState *env =3D cpu_env(cs); - int do_irq =3D cpu_test_interrupt(cs, INT_FLAGS); uint32_t save_psw; =20 env->in_sleep =3D 0; @@ -57,27 +55,24 @@ void rx_cpu_do_interrupt(CPUState *cs) save_psw =3D rx_cpu_pack_psw(env); env->psw_pm =3D env->psw_i =3D env->psw_u =3D 0; =20 - if (do_irq) { - if (do_irq & CPU_INTERRUPT_FIR) { - env->bpc =3D env->pc; - env->bpsw =3D save_psw; - env->pc =3D env->fintv; - env->psw_ipl =3D 15; - cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); - qemu_set_irq(env->ack, env->ack_irq); - qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); - } else if (do_irq & CPU_INTERRUPT_HARD) { - env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); - env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); - env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); - env->psw_ipl =3D env->ack_ipl; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - qemu_set_irq(env->ack, env->ack_irq); - qemu_log_mask(CPU_LOG_INT, - "interrupt 0x%02x raised\n", env->ack_irq); - } + if (cpu_test_interrupt(cs, CPU_INTERRUPT_FIR)) { + env->bpc =3D env->pc; + env->bpsw =3D save_psw; + env->pc =3D env->fintv; + env->psw_ipl =3D 15; + cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); + qemu_set_irq(env->ack, env->ack_irq); + qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); + } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { + env->isp -=3D 4; + cpu_stl_data(env, env->isp, save_psw); + env->isp -=3D 4; + cpu_stl_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); + env->psw_ipl =3D env->ack_ipl; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + qemu_set_irq(env->ack, env->ack_irq); + qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_i= rq); } else { uint32_t vec =3D cs->exception_index; const char *expname =3D "unknown exception"; --=20 2.47.3