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Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org Subject: [PULL 5/7] hw/nvme: connect SPDM over NVMe Security Send/Recv Date: Thu, 30 Oct 2025 08:29:53 +0100 Message-ID: <20251030072956.1194-6-its@irrelevant.dk> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251030072956.1194-1-its@irrelevant.dk> References: <20251030072956.1194-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.149; envelope-from=its@irrelevant.dk; helo=fout-a6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @irrelevant.dk) X-ZM-MESSAGEID: 1761809526005158500 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch extends the existing support we have for NVMe with only DoE to also add support to SPDM over the NVMe Security Send/Recv commands. With the new definition of the `spdm-trans` argument, users can specify `spdm_trans=3Dnvme` or `spdm_trans=3Ddoe`. This allows us to select the SPDM transport respectively. SPDM over the NVMe Security Send/Recv commands are defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa Reviewed-by: Jonathan Cameron Reviewed-by: Klaus Jensen Reviewed-by: Alistair Francis [k.jensen: fix declaration in case statement; fix quotes in docs] Signed-off-by: Klaus Jensen --- docs/specs/spdm.rst | 10 ++++++-- hw/nvme/ctrl.c | 47 ++++++++++++++++++++++++++++--------- include/hw/pci/pci_device.h | 2 ++ 3 files changed, 46 insertions(+), 13 deletions(-) diff --git a/docs/specs/spdm.rst b/docs/specs/spdm.rst index 0e3ad25bc698..477ff9ef36c7 100644 --- a/docs/specs/spdm.rst +++ b/docs/specs/spdm.rst @@ -98,7 +98,7 @@ Then you can add this to your QEMU command line: .. code-block:: shell =20 -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe =20 At which point QEMU will try to connect to the SPDM server. =20 @@ -113,7 +113,13 @@ of the default. So the entire QEMU command might look = like this -append "root=3D/dev/vda console=3DttyS0" \ -net none -nographic \ -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe + +The ``spdm_trans`` argument defines the underlying transport type that is +emulated by QEMU. For an PCIe NVMe controller, both "doe" and "nvme" are +supported. Where, "doe" does SPDM transport over the PCIe extended capabil= ity +Data Object Exchange (DOE), and "nvme" uses the NVMe Admin Security +Send/Receive commands to implement the SPDM transport. =20 .. _DMTF: https://www.dmtf.org/standards/SPDM diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index e450e785ea10..fa003031e719 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8943,19 +8943,33 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev, Error **errp) =20 pcie_cap_deverr_init(pci_dev); =20 - /* DOE Initialisation */ + /* SPDM Initialisation */ if (pci_dev->spdm_port) { - uint16_t doe_offset =3D n->params.sriov_max_vfs ? - PCI_CONFIG_SPACE_SIZE + PCI_ARI_SIZEOF - : PCI_CONFIG_SPACE_SIZE; + uint16_t doe_offset =3D PCI_CONFIG_SPACE_SIZE; =20 - pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, - doe_spdm_prot, true, 0); + switch (pci_dev->spdm_trans) { + case SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE: + if (n->params.sriov_max_vfs) { + doe_offset +=3D PCI_ARI_SIZEOF; + } =20 - pci_dev->doe_spdm.spdm_socket =3D spdm_socket_connect(pci_dev->spd= m_port, - errp); + pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, + doe_spdm_prot, true, 0); =20 - if (pci_dev->doe_spdm.spdm_socket < 0) { + pci_dev->doe_spdm.spdm_socket =3D + spdm_socket_connect(pci_dev->spdm_port, errp); + + if (pci_dev->doe_spdm.spdm_socket < 0) { + return false; + } + break; + case SPDM_SOCKET_TRANSPORT_TYPE_NVME: + n->spdm_socket =3D spdm_socket_connect(pci_dev->spdm_port, err= p); + if (n->spdm_socket < 0) { + return false; + } + break; + default: return false; } } @@ -9246,9 +9260,14 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cmb.buf); } =20 + /* Only one of the `spdm_socket`s below should have been setup */ + assert(!(pci_dev->doe_spdm.spdm_socket > 0 && n->spdm_socket >=3D 0)); if (pci_dev->doe_spdm.spdm_socket > 0) { spdm_socket_close(pci_dev->doe_spdm.spdm_socket, SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE); + } else if (n->spdm_socket >=3D 0) { + spdm_socket_close(pci_dev->doe_spdm.spdm_socket, + SPDM_SOCKET_TRANSPORT_TYPE_NVME); } =20 if (n->pmr.dev) { @@ -9303,6 +9322,8 @@ static const Property nvme_props[] =3D { false), DEFINE_PROP_UINT16("mqes", NvmeCtrl, params.mqes, 0x7ff), DEFINE_PROP_UINT16("spdm_port", PCIDevice, spdm_port, 0), + DEFINE_PROP_SPDM_TRANS("spdm_trans", PCIDevice, spdm_trans, + SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE), DEFINE_PROP_BOOL("ctratt.mem", NvmeCtrl, params.ctratt.mem, false), DEFINE_PROP_BOOL("atomic.dn", NvmeCtrl, params.atomic_dn, 0), DEFINE_PROP_UINT16("atomic.awun", NvmeCtrl, params.atomic_awun, 0), @@ -9378,7 +9399,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, { uint16_t old_num_vfs =3D pcie_sriov_num_vfs(dev); =20 - if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + /* DOE is only initialised if SPDM over DOE is used */ + if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + dev->spdm_trans =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE) { pcie_doe_write_config(&dev->doe_spdm, address, val, len); } pci_default_write_config(dev, address, val, len); @@ -9389,7 +9412,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, static uint32_t nvme_pci_read_config(PCIDevice *dev, uint32_t address, int= len) { uint32_t val; - if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + + if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + (dev->spdm_trans =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE)) { if (pcie_doe_read_config(&dev->doe_spdm, address, len, &val)) { return val; } diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index eee03385686c..88ccea501136 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -4,6 +4,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_doe.h" +#include "system/spdm-socket.h" =20 #define TYPE_PCI_DEVICE "pci-device" typedef struct PCIDeviceClass PCIDeviceClass; @@ -166,6 +167,7 @@ struct PCIDevice { =20 /* SPDM */ uint16_t spdm_port; + SpdmTransportType spdm_trans; =20 /* DOE */ DOECap doe_spdm; --=20 2.51.0