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Wed, 29 Oct 2025 15:07:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PULL 23/23] hw/riscv: Replace target_ulong uses Date: Wed, 29 Oct 2025 22:40:00 +0100 Message-ID: <20251029214001.99824-24-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029214001.99824-1-philmd@linaro.org> References: <20251029214001.99824-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761775800758154100 From: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Anton Johansson Message-ID: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/riscv-iommu.c | 6 ++++-- hw/riscv/riscv_hart.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index b33c7fe3259..f8656ec04b1 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -26,6 +26,8 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/timer.h" +#include "qemu/target-info.h" +#include "qemu/bitops.h" =20 #include "cpu_bits.h" #include "riscv-iommu.h" @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx, const uint64_t va_mask =3D (1ULL << va_len) - 1; =20 if (pass =3D=3D S_STAGE && va_len > 32) { - target_ulong mask, masked_msbs; + uint64_t mask, masked_msbs; =20 - mask =3D (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1; + mask =3D MAKE_64BIT_MASK(0, target_long_bits() - va_len + = 1); masked_msbs =3D (addr >> (va_len - 1)) & mask; =20 if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 4d51a93dd52..33cbc9873e6 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -94,7 +94,7 @@ static bool csr_qtest_callback(CharFrontend *chr, gchar *= *words) g_assert(rc =3D=3D 0); csr_call(words[1], cpu, csr, &val); =20 - qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); + qtest_sendf(chr, "OK 0 %"PRIx64"\n", val); =20 return true; } --=20 2.51.0