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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.78.162; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761759440067158500 Content-Type: text/plain; charset="utf-8" Switch its to a tristate. Windows Hypervisor Platform's vGIC doesn't support ITS. Deal with this by reporting to the user and exiting. Regular configuration: GICv3 + ITS New default configuration with WHPX: GICv3 with GICv2m And its=3Doff explicitly for the newest machine version: GICv3 + GICv2m Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 15 +++++++------ hw/arm/virt.c | 46 +++++++++++++++++++++++++++++++--------- include/hw/arm/virt.h | 4 +++- 3 files changed, 47 insertions(+), 18 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0a6ec74aa0..8e730731ca 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -472,7 +472,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -483,7 +483,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc_mapping_count +=3D rc_its_idmaps->len; } } else { - if (vms->its) { + if (virt_is_its_enabled(vms)) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -498,7 +498,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -517,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -610,7 +610,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. @@ -945,7 +945,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -961,7 +961,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) && !vms->n= o_gicv3_with_gicv2m) { + if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(= vms)) + && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9121eb37eb..dbf9a28b8d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -735,7 +735,7 @@ static void create_its(VirtMachineState *vms) { DeviceState *dev; =20 - assert(vms->its); + assert(virt_is_its_enabled(vms)); if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { /* * Do nothing if ITS is neither supported by the host nor emulated= by @@ -744,6 +744,15 @@ static void create_its(VirtMachineState *vms) return; } =20 + if (whpx_enabled() && vms->tcg_its) { + /* + * Signal to the user when ITS is neither supported by the host + * nor emulated by the machine. + */ + info_report("ITS not supported on WHPX."); + exit(1); + } + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), @@ -955,7 +964,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(vm= s)) { create_its(vms); } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { create_v2m(vms); @@ -2705,18 +2714,34 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 -static bool virt_get_its(Object *obj, Error **errp) +bool virt_is_its_enabled(VirtMachineState *vms) +{ + if (vms->its =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + if (vms->its =3D=3D ON_OFF_AUTO_AUTO) { + if (whpx_enabled()) { + return false; + } + } + return true; +} + +static void virt_get_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); + OnOffAuto its =3D vms->its; =20 - return vms->its; + visit_type_OnOffAuto(v, name, &its, errp); } =20 -static void virt_set_its(Object *obj, bool value, Error **errp) +static void virt_set_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - vms->its =3D value; + visit_type_OnOffAuto(v, name, &vms->its, errp); } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3426,8 +3451,9 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 - object_class_property_add_bool(oc, "its", virt_get_its, - virt_set_its); + object_class_property_add(oc, "its", "OnOffAuto", + virt_get_its, virt_set_its, + NULL, NULL); object_class_property_set_description(oc, "its", "Set on/off to enable/disable " "ITS instantiation"); @@ -3487,8 +3513,8 @@ static void virt_instance_init(Object *obj) vms->highmem_mmio =3D true; vms->highmem_redists =3D true; =20 - /* Default allows ITS instantiation */ - vms->its =3D true; + /* Default allows ITS instantiation if available */ + vms->its =3D ON_OFF_AUTO_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; vms->no_gicv3_with_gicv2m =3D false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d31348dd61..997dd51678 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -149,7 +149,7 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; - bool its; + OnOffAuto its; bool tcg_its; bool virt; bool ras; @@ -218,4 +218,6 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +bool virt_is_its_enabled(VirtMachineState *vms); + #endif /* QEMU_ARM_VIRT_H */ --=20 2.50.1 (Apple Git-155)