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Wed, 29 Oct 2025 08:57:34 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Julian Ganz , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PULL 30/35] tests: add test for double-traps on rv64 Date: Wed, 29 Oct 2025 15:50:39 +0000 Message-ID: <20251029155045.257802-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251029155045.257802-1-alex.bennee@linaro.org> References: <20251029155045.257802-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761753554027154100 From: Julian Ganz We do have a number of test-case for various architectures exercising their interrupt/exception logic. However, for the recently introduced trap API we also want to exercise the logic for double traps on at least one architecture. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Julian Ganz Message-ID: <20251027110344.2289945-31-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 3ca595335dd..d9c0036eb4b 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -24,5 +24,11 @@ EXTRA_RUNS +=3D run-test-mepc-masking run-test-mepc-masking: test-mepc-masking $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) =20 +EXTRA_RUNS +=3D run-plugin-doubletrap +run-plugin-doubletrap: doubletrap + $(call run-test, $<, \ + $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \ + $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/doubletrap.S b/tests/tcg/riscv64/doubletrap.S new file mode 100644 index 00000000000..b61089c9c1c --- /dev/null +++ b/tests/tcg/riscv64/doubletrap.S @@ -0,0 +1,73 @@ + .option norvc + + .text + .global _start +_start: + # Set up vectored interrupts + lla t0, trap + add t0, t0, 1 + csrw mtvec, t0 + + # Enable sw interrupts + csrrsi zero, mie, 0x8 + csrrsi zero, mstatus, 0x8 + + # Engage the double trap: we trigger an machine-level software + # interrupt, which will trap to an illegal instruction + lui t1, 0x02000 + li t0, 1 + sw t0, 0(t1) + + # If we still not went out via the software interrupt route after a + # short while, we failed the test. + lui t0, 0x1 +0: + addi t0, t0, -1 + bnez t0, 0b + j fail + +trap: + j illegal_insn # Exceptions + j fail # Supervisor software interrupt + j fail + .insn i CUSTOM_0, 0, x0, x0, 0 # Machine software interrupt + j fail + j fail # Supervisor timer interrupt + j fail + j fail # Machine timer interrupt + j fail + j fail # Supervisor external interrupt + j fail + j fail # Machine external interrupt + j fail + j fail # Counter overflow interrupt + j fail + j fail + +illegal_insn: + # Check whether we really got an illegal instruction + csrr t0, mcause + li t1, 2 + bne t0, t1, fail + li a0, 0 + j _exit +fail: + li a0, 1 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 --=20 2.47.3