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Wed, 29 Oct 2025 08:57:29 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Julian Ganz , Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PULL 22/35] target/riscv: call plugin trap callbacks Date: Wed, 29 Oct 2025 15:50:31 +0000 Message-ID: <20251029155045.257802-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251029155045.257802-1-alex.bennee@linaro.org> References: <20251029155045.257802-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761753708811158500 From: Julian Ganz We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for RISC-V targets. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Julian Ganz Message-ID: <20251027110344.2289945-23-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 360db133e21..c4fb68b5de8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -36,6 +36,7 @@ #include "cpu_bits.h" #include "debug.h" #include "pmp.h" +#include "qemu/plugin.h" =20 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { @@ -2175,6 +2176,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; const bool prev_virt =3D env->virt_enabled; const target_ulong prev_priv =3D env->priv; + uint64_t last_pc =3D env->pc; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -2197,6 +2199,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc +=3D 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; #endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: @@ -2466,6 +2469,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) prev_priv, prev_virt); } =20 + if (async) { + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + } else { + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } + /* * Interrupt/exception/trap delivery is asynchronous event and as per * zicfilp spec CPU should clear up the ELP state. No harm in clearing --=20 2.47.3