From nobody Fri Nov 14 19:34:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1761764969; cv=none; d=zohomail.com; s=zohoarc; b=Ez32Do0J5Rrs2Imw4OqAxv6HaB4+2/Bkc5uXi7nVtlxRkquYUEch7ZuSavLTin9JC0H9dP0vlR71U3EvR6P9h7jE7rFwIH+YtDO9vys3H9LzvqAZB6wblsXih4wNwxNWgHEFO4CQnFudpvNu6uESa5d0doB4ov0QcElbCx+ccmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761764969; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XnC9Njsa3+9pTSXEc6m+ZkC6y8BZ0W+4yH/alKcG3dY=; b=GOqm/wY50tYAfSFbp3ZkItzkgUhsMmBTn37pIUZwEVCcXWGUYyAWbYRE8xbhW8kKzBGm58JXcDyQI4+a4iaCXUZxprgzaHc3N+3jxkcTR9t2Q4DiTQYcPikFt5oabPrxxBGZydRmirASYwcuFex4ajU4vuF7LTD5jUde5odEK3A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761764969306500.10162633624077; Wed, 29 Oct 2025 12:09:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vEBW5-0006Kd-M4; Wed, 29 Oct 2025 15:07:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vEBW3-0006KJ-RA; Wed, 29 Oct 2025 15:07:27 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vEBVu-0001Or-QS; Wed, 29 Oct 2025 15:07:27 -0400 Received: from pps.filterd (m0353725.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59TBMOi8001087; Wed, 29 Oct 2025 19:07:08 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4a34ajmwm5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Oct 2025 19:07:07 +0000 (GMT) Received: from m0353725.ppops.net (m0353725.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 59TJ77RF012924; Wed, 29 Oct 2025 19:07:07 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4a34ajmwm3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Oct 2025 19:07:07 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 59TGncxo023836; Wed, 29 Oct 2025 19:07:06 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4a33vx5117-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Oct 2025 19:07:06 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 59TJ72Lg42402228 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Oct 2025 19:07:02 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB03620049; Wed, 29 Oct 2025 19:07:02 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 72EBE20040; Wed, 29 Oct 2025 19:07:01 +0000 (GMT) Received: from ltcd48-lp3.ltc.tadn.ibm.com (unknown [9.5.7.39]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 29 Oct 2025 19:07:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=XnC9Njsa3+9pTSXEc 6m+ZkC6y8BZ0W+4yH/alKcG3dY=; b=tHTtuhFahZZXv66M4VgIXc87R150e4IOq Xb/Da2lq2hv0Y07C1oJKD+1acwxIaVjg11rmIbz42hE4u4Z8wn5byBCYjYf6yema oSMVOgc6MqjnOV/5G0tupuRb6jw8Df8fUaofP5aLxTceIbRNxa9CSGW+ML+JlWZj zY1lPurmy+qfTMxqZ6y7sqAmYzvyLJPmNEvcyyvON9jS+ZrDnda9m2W6razd8KFu qYKcArXgbvfBo8cTA+dPBn8vpTDPDcodoROkXlTc5Vfr+WAae+QGyrFChn7u6gft SET+QR/7q4ypu54Vjxr5zxH7/5LraQfRwZ86NWCqUArzZnswK3eyA== From: Narayana Murty N To: npiggin@gmail.com, harshpb@linux.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: mahesh@linux.ibm.com, ganeshgr@linux.ibm.com Subject: [RFC 1/4] ppc/spapr: Add VFIO EEH error injection backend Date: Wed, 29 Oct 2025 10:06:15 -0500 Message-ID: <20251029150618.186803-2-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029150618.186803-1-nnmlinux@linux.ibm.com> References: <20251029150618.186803-1-nnmlinux@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=C/XkCAP+ c=1 sm=1 tr=0 ts=690265db cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=qkVa7TRde7xkgx6zoNMA:9 X-Proofpoint-GUID: VXeibnPKf9mI4t4SC0aY4s6lBNbIYe33 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDE2NiBTYWx0ZWRfX4MfGKr7bKyAk vja9ZlzfdEjCNC4+08IScrJgWI5ED7y4QmVNr067NIzYHIk/7BfFHWo3Udl143zuO/s+k4sF+L/ NpmO0cUe9WiERA6bkkU+YMiwaf/GCEJH52N4ondRWzgKNrjZiqdxBHiBIp7sgW/Uajh63oqWdAm /Cfu5MZXoXBEAhdaDSd5wRoj3qx3wJPWhRPVMfKbVPYJgVTcfJY54tFaXWKRf1FGO1FRiqLf97O q3fmsYrpsatEKeULyMXnlBgV+oz6FkjPEJB1BjSXT2paC0tdHYKv9LaTOPJQDXRRe/vwhfUEdDQ RpKLsKu1F+6XUw3B5iBjCNCz3/T7evu7WL79SkJ9yCZsMb7A5W99q574NPGFbHMCO1I9PD9Xep4 g16paMtZy88tijjCccdJha9i+DaVcw== X-Proofpoint-ORIG-GUID: jPeWKrkU85FZZpuorzGlnP_9nX9lOCrK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-29_07,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 clxscore=1011 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2510280166 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nnmlinux@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1761764972182154100 Content-Type: text/plain; charset="utf-8" Introduce 'spapr_phb_vfio_errinjct()' to inject PCI PHB error events via the VFIO passthrough backend. This function translates RTAS error injection parameters into VFIO EEH injection commands suitable for hardware emulation. The patch adds: - A minimal 'enum rtas_err_type' for error types used in VFIO path - EEH function code macros ('EEH_ERR_FUNC_...') - Backend stub and integration into 'spapr_pci_vfio.c' - Necessary header declarations for interfacing This forms the foundational layer for PCI error injection testing using VFIO passthrough devices on pseries guests. Signed-off-by: Narayana Murty N --- include/hw/pci-host/spapr.h | 7 +++++ include/hw/ppc/spapr.h | 44 ++++++++++++++++++++++++++++++ hw/ppc/spapr_pci_vfio.c | 53 +++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 0db87f1281..2e91e0fb38 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -125,6 +125,8 @@ int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, i= nt *state); int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t func, + uint64_t addr, uint64_t mask, uint32_t type); #else static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) { @@ -151,6 +153,11 @@ static inline int spapr_phb_vfio_eeh_configure(SpaprPh= bState *sphb) static inline void spapr_phb_vfio_reset(DeviceState *qdev) { } +static int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, uint32_t func, + uint64_t addr, uint64_t mask, uint32_t = type) +{ + return RTAS_OUT_HW_ERROR; +} #endif =20 void spapr_phb_dma_reset(SpaprPhbState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 39bd5bd5ed..331946ee57 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -691,6 +691,50 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr); #define RTAS_EEH_PE_UNAVAIL_INFO 1000 #define RTAS_EEH_PE_RECOVER_INFO 0 =20 +/* EEH error types and functions */ +#define EEH_ERR_FUNC_MIN 0 +#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ +#define EEH_ERR_FUNC_LD_MEM_DATA 1 +#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ +#define EEH_ERR_FUNC_LD_IO_DATA 3 +#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ +#define EEH_ERR_FUNC_LD_CFG_DATA 5 +#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ +#define EEH_ERR_FUNC_ST_MEM_DATA 7 +#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ +#define EEH_ERR_FUNC_ST_IO_DATA 9 +#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ +#define EEH_ERR_FUNC_ST_CFG_DATA 11 +#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ +#define EEH_ERR_FUNC_DMA_RD_DATA 13 +#define EEH_ERR_FUNC_DMA_RD_MASTER 14 +#define EEH_ERR_FUNC_DMA_RD_TARGET 15 +#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ +#define EEH_ERR_FUNC_DMA_WR_DATA 17 +#define EEH_ERR_FUNC_DMA_WR_MASTER 18 +#define EEH_ERR_FUNC_DMA_WR_TARGET 19 +#define EEH_ERR_FUNC_MAX EEH_ERR_FUNC_DMA_WR_TARGET + +/* RTAS PCI Error Injection Token Types */ +enum rtas_err_type { + RTAS_ERR_TYPE_FATAL =3D 0x1, + RTAS_ERR_TYPE_RECOVERED_RANDOM_EVENT =3D 0x2, + RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT =3D 0x3, + RTAS_ERR_TYPE_CORRUPTED_PAGE =3D 0x4, + RTAS_ERR_TYPE_CORRUPTED_SLB =3D 0x5, + RTAS_ERR_TYPE_TRANSLATOR_FAILURE =3D 0x6, + RTAS_ERR_TYPE_IOA_BUS_ERROR =3D 0x7, + RTAS_ERR_TYPE_PLATFORM_SPECIFIC =3D 0x8, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_START =3D 0x9, + RTAS_ERR_TYPE_CORRUPTED_DCACHE_END =3D 0xA, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_START =3D 0xB, + RTAS_ERR_TYPE_CORRUPTED_ICACHE_END =3D 0xC, + RTAS_ERR_TYPE_CORRUPTED_TLB_START =3D 0xD, + RTAS_ERR_TYPE_CORRUPTED_TLB_END =3D 0xE, + RTAS_ERR_TYPE_IOA_BUS_ERROR_64 =3D 0xF, + RTAS_ERR_TYPE_UPSTREAM_IO_ERROR =3D 0x10 +}; + /* ibm,set-slot-reset */ #define RTAS_SLOT_RESET_DEACTIVATE 0 #define RTAS_SLOT_RESET_HOT 1 diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index a748a0bf4c..ed0b22a84a 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -317,6 +317,55 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_SUCCESS; } =20 +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, + uint32_t func, uint64_t addr, + uint64_t mask, uint32_t type) +{ + VFIOLegacyContainer *container =3D vfio_eeh_as_container(&sphb->iommu_= as); + struct vfio_eeh_pe_op op =3D { + .op =3D VFIO_EEH_PE_INJECT_ERR, + .argsz =3D sizeof(op), + }; + + /* Set error type, address, and mask */ + op.err.type =3D type; + op.err.addr =3D addr; + op.err.mask =3D mask; + + /* Validate and set function code */ + switch (func) { + case EEH_ERR_FUNC_LD_MEM_ADDR: + case EEH_ERR_FUNC_LD_MEM_DATA: + case EEH_ERR_FUNC_LD_IO_ADDR: + case EEH_ERR_FUNC_LD_IO_DATA: + case EEH_ERR_FUNC_LD_CFG_ADDR: + case EEH_ERR_FUNC_LD_CFG_DATA: + case EEH_ERR_FUNC_ST_MEM_ADDR: + case EEH_ERR_FUNC_ST_MEM_DATA: + case EEH_ERR_FUNC_ST_IO_ADDR: + case EEH_ERR_FUNC_ST_IO_DATA: + case EEH_ERR_FUNC_ST_CFG_ADDR: + case EEH_ERR_FUNC_ST_CFG_DATA: + case EEH_ERR_FUNC_DMA_RD_ADDR: + case EEH_ERR_FUNC_DMA_RD_DATA: + case EEH_ERR_FUNC_DMA_RD_MASTER: + case EEH_ERR_FUNC_DMA_RD_TARGET: + case EEH_ERR_FUNC_DMA_WR_ADDR: + case EEH_ERR_FUNC_DMA_WR_DATA: + case EEH_ERR_FUNC_DMA_WR_MASTER: + op.err.func =3D func; + break; + default: + return RTAS_OUT_PARAM_ERROR; + } + + /* Perform the ioctl to inject the error */ + if (ioctl(container->fd, VFIO_EEH_PE_OP, &op) < 0) { + return RTAS_OUT_HW_ERROR; + } + + return RTAS_OUT_SUCCESS; +} #else =20 bool spapr_phb_eeh_available(SpaprPhbState *sphb) @@ -349,4 +398,8 @@ int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) return RTAS_OUT_NOT_SUPPORTED; } =20 +int spapr_phb_vfio_errinjct(SpaprPhbState *sphb, int option) +{ + return RTAS_OUT_NOT_SUPPORTED; +} #endif /* CONFIG_VFIO_PCI */ --=20 2.51.0