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Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 18 ++++++++++++++++++ hw/arm/fsl-imx8mp.c | 33 ++++++++++++++++++++++++++++----- hw/arm/imx8mp-evk.c | 12 ++++++++++++ hw/arm/Kconfig | 3 ++- 4 files changed, 60 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index b2f7d29ade..ccf81381b1 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -60,3 +60,21 @@ Now that everything is prepared the machine can be start= ed as follows: -dtb imx8mp-evk.dtb \ -append "root=3D/dev/mmcblk2p2" \ -drive file=3Dsdcard.img,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmcblk2 + + +KVM Acceleration +---------------- + +To enable hardware-assisted acceleration via KVM, append +``-accel kvm -cpu host`` to the command line. While this speeds up perform= ance +significantly, be aware of the following limitations: + +* Unlike other machines with KVM support, the ``imx8mp-evk`` machine makes= no + attempt to protect itself from malicious guests. If you don't trust your + guests and you're relying on QEMU to be the security boundary, you want = to + choose another machine such as ``virt``. +* Rather than Cortex-A53 CPUs, the same CPU type as the host's will be use= d. + This is a limitation of KVM and may not work with guests with a tight + dependency on Cortex-A53. +* No EL2 and EL3 exception levels are available which is also a KVM limita= tion. + Direct kernel boot should work but running U-Boot, TF-A, etc. won't succ= eed. diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 866f4d1d74..7e61392abb 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -12,11 +12,13 @@ #include "system/address-spaces.h" #include "hw/arm/bsa.h" #include "hw/arm/fsl-imx8mp.h" -#include "hw/intc/arm_gicv3.h" #include "hw/misc/unimp.h" #include "hw/boards.h" +#include "system/kvm.h" #include "system/system.h" +#include "target/arm/cpu.h" #include "target/arm/cpu-qom.h" +#include "target/arm/kvm_arm.h" #include "qapi/error.h" #include "qobject/qlist.h" =20 @@ -197,11 +199,10 @@ static void fsl_imx8mp_init(Object *obj) =20 for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX8MP_NUM_CPUS); i++) { g_autofree char *name =3D g_strdup_printf("cpu%d", i); - object_initialize_child(obj, name, &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a53")); + object_initialize_child(obj, name, &s->cpu[i], ms->cpu_type); } =20 - object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3); + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); =20 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM); =20 @@ -274,7 +275,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) /* CPUs */ for (i =3D 0; i < ms->smp.cpus; i++) { /* On uniprocessor, the CBAR is set to 0 */ - if (ms->smp.cpus > 1) { + if (ms->smp.cpus > 1 && + object_property_find(OBJECT(&s->cpu[i]), "reset-cbar")) { object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST]= .addr, &error_abort); @@ -286,6 +288,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, &error_abort); =20 + if (object_property_find(OBJECT(&s->cpu[i]), "has_el2")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el2", + !kvm_enabled(), &error_abort); + } + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", + !kvm_enabled(), &error_abort); + } + if (i) { /* * Secondary CPUs start in powered-down state (and can be @@ -304,6 +316,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) { SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); QList *redist_region_count; + bool pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NU= LL); =20 qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus); qdev_prop_set_uint32(gicdev, "num-irq", @@ -360,6 +373,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + if (kvm_enabled()) { + if (pmu) { + assert(arm_feature(&s->cpu[i].env, ARM_FEATURE_PMU)); + if (kvm_irqchip_in_kernel()) { + kvm_arm_pmu_set_irq(&s->cpu[i], VIRTUAL_PMU_IRQ); + } + kvm_arm_pmu_init(&s->cpu[i]); + } + } } } =20 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index b3082fa60d..80036f8589 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -12,6 +12,7 @@ #include "hw/arm/fsl-imx8mp.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "system/kvm.h" #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -93,11 +94,22 @@ static void imx8mp_evk_init(MachineState *machine) } } =20 +static const char *imx8mp_evk_get_default_cpu_type(const MachineState *ms) +{ + if (kvm_enabled()) { + return ARM_CPU_TYPE_NAME("host"); + } + + return ARM_CPU_TYPE_NAME("cortex-a53"); +} + static void imx8mp_evk_machine_init(MachineClass *mc) { mc->desc =3D "NXP i.MX 8M Plus EVK Board"; mc->init =3D imx8mp_evk_init; mc->max_cpus =3D FSL_IMX8MP_NUM_CPUS; mc->default_ram_id =3D "imx8mp-evk.ram"; + mc->get_default_cpu_type =3D imx8mp_evk_get_default_cpu_type; } + DEFINE_MACHINE("imx8mp-evk", imx8mp_evk_machine_init) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b44b85f436..0cdeb60f1f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -622,7 +622,8 @@ config FSL_IMX8MP config FSL_IMX8MP_EVK bool default y - depends on TCG && AARCH64 + depends on AARCH64 + depends on TCG || KVM select FSL_IMX8MP =20 config ARM_SMMUV3 --=20 2.51.2