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charset="utf-8" HOST_DATA as a source for 2D blits (ROP3_SRCCOPY) was unimplemented, preventing X.org text rendering with 2D acceleration enabled. This implements monochrome HOST_DATA blits with color expansion, enabling xterm to render text correctly. The blit itself has been implemented as a separate function to keep things focused. Future work could refactor this, and the existing blits, to use shared helpers for common patterns. Changes: - Add clipping register handlers (SC_TOP_LEFT, SC_BOTTOM_RIGHT, SRC_SC_BOTTOM_RIGHT) and defaulting - Add DP_SRC_FRGD_CLR and DP_SRC_BKGD_CLR register write handlers to enable color expansion - Implement expand_colors() to convert 1bpp monochrome data to 32bpp color - Add ati_blt_mono_host_to_screen() for monochrome HOST_DATA blits The host data buffer has a fixed 4MiB size. This _should_ cover typical use cases and overflow is logged. Future work could implement dynamic allocation based on blit dimensions. Tested on Rage 128. From what I understand the R100 also shares these registers but that device has not been tested against Xorg. There seem to be other issues preventing Xorg from starting with the radeon driver. Note: The xorg/xf86-video-r128 drivers support both CCE (DMA) and MMIO acceleration. This implements MMIO, which the driver uses when built with --disable-dri. CCE of course is another can of worms. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 78 ++++++++++++++++++++++++++++-- hw/display/ati_2d.c | 110 +++++++++++++++++++++++++++++++++++++++++- hw/display/ati_dbg.c | 9 ++++ hw/display/ati_int.h | 6 +++ hw/display/ati_regs.h | 28 ++++++++++- 5 files changed, 223 insertions(+), 8 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index f7c0006a87..1dfaa79202 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -510,6 +510,15 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) case DEFAULT_SC_BOTTOM_RIGHT: val =3D s->regs.default_sc_bottom_right; break; + case SC_TOP_LEFT: + val =3D s->regs.sc_top_left; + break; + case SC_BOTTOM_RIGHT: + val =3D s->regs.sc_bottom_right; + break; + case SRC_SC_BOTTOM_RIGHT: + val =3D s->regs.src_sc_bottom_right; + break; default: break; } @@ -804,9 +813,14 @@ static void ati_mm_write(void *opaque, hwaddr addr, } break; case DST_WIDTH: + { + uint32_t src =3D s->regs.dp_gui_master_cntl & GMC_SRC_SOURCE_MASK; s->regs.dst_width =3D data & 0x3fff; - ati_2d_blt(s); + if (src !=3D GMC_SRC_SOURCE_HOST_DATA) { + ati_2d_blt(s); + } break; + } case DST_HEIGHT: s->regs.dst_height =3D data & 0x3fff; break; @@ -853,21 +867,39 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dst_y =3D (data >> 16) & 0x3fff; break; case DST_HEIGHT_WIDTH: + { + uint32_t src =3D s->regs.dp_gui_master_cntl & GMC_SRC_SOURCE_MASK; s->regs.dst_width =3D data & 0x3fff; s->regs.dst_height =3D (data >> 16) & 0x3fff; - ati_2d_blt(s); + if (src !=3D GMC_SRC_SOURCE_HOST_DATA) { + ati_2d_blt(s); + } break; + } case DP_GUI_MASTER_CNTL: - s->regs.dp_gui_master_cntl =3D data & 0xf800000f; + s->regs.dp_gui_master_cntl =3D data & 0xff80000f; s->regs.dp_datatype =3D (data & 0x0f00) >> 8 | (data & 0x30f0) << = 4 | (data & 0x4000) << 16; s->regs.dp_mix =3D (data & GMC_ROP3_MASK) | (data & 0x7000000) >> = 16; + + if ((data & GMC_SRC_CLIPPING_MASK) =3D=3D GMC_SRC_CLIP_DEFAULT) { + s->regs.src_sc_bottom_right =3D s->regs.default_sc_bottom_righ= t; + } + if ((data & GMC_DST_CLIPPING_MASK) =3D=3D GMC_DST_CLIP_DEFAULT) { + s->regs.sc_top_left =3D 0; + s->regs.sc_bottom_right =3D s->regs.default_sc_bottom_right; + } break; case DST_WIDTH_X: + { + uint32_t src =3D s->regs.dp_gui_master_cntl & GMC_SRC_SOURCE_MASK; s->regs.dst_x =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; - ati_2d_blt(s); + if (src !=3D GMC_SRC_SOURCE_HOST_DATA) { + ati_2d_blt(s); + } break; + } case SRC_X_Y: s->regs.src_y =3D data & 0x3fff; s->regs.src_x =3D (data >> 16) & 0x3fff; @@ -877,10 +909,15 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dst_x =3D (data >> 16) & 0x3fff; break; case DST_WIDTH_HEIGHT: + { + uint32_t src =3D s->regs.dp_gui_master_cntl & GMC_SRC_SOURCE_MASK; s->regs.dst_height =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; - ati_2d_blt(s); + if (src !=3D GMC_SRC_SOURCE_HOST_DATA) { + ati_2d_blt(s); + } break; + } case DST_HEIGHT_Y: s->regs.dst_y =3D data & 0x3fff; s->regs.dst_height =3D (data >> 16) & 0x3fff; @@ -909,6 +946,12 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DP_CNTL: s->regs.dp_cntl =3D data; break; + case DP_SRC_FRGD_CLR: + s->regs.dp_src_frgd_clr =3D data; + break; + case DP_SRC_BKGD_CLR: + s->regs.dp_src_bkgd_clr =3D data; + break; case DP_DATATYPE: s->regs.dp_datatype =3D data & 0xe0070f0f; break; @@ -937,6 +980,29 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DEFAULT_SC_BOTTOM_RIGHT: s->regs.default_sc_bottom_right =3D data & 0x3fff3fff; break; + case SC_TOP_LEFT: + s->regs.sc_top_left =3D data; + break; + case SC_BOTTOM_RIGHT: + s->regs.sc_bottom_right =3D data; + break; + case SRC_SC_BOTTOM_RIGHT: + s->regs.src_sc_bottom_right =3D data; + break; + case HOST_DATA0 ... HOST_DATA7: + case HOST_DATA_LAST: + if (s->host_data_pos + 4 > sizeof(s->host_data_buffer)) { + qemu_log_mask(LOG_UNIMP, "HOST_DATA buffer overflow " + "(buffer size: %zu bytes)\n", + sizeof(s->host_data_buffer)); + return; + } + stn_he_p(&s->host_data_buffer[s->host_data_pos], 4, data); + s->host_data_pos +=3D 4; + if (addr =3D=3D HOST_DATA_LAST) { + ati_2d_blt(s); + } + break; default: break; } @@ -1018,6 +1084,7 @@ static void ati_vga_realize(PCIDevice *dev, Error **e= rrp) /* most interrupts are not yet emulated but MacOS needs at least VBlan= k */ dev->config[PCI_INTERRUPT_PIN] =3D 1; timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq= , s); + s->host_data_pos =3D 0; } =20 static void ati_vga_reset(DeviceState *dev) @@ -1030,6 +1097,7 @@ static void ati_vga_reset(DeviceState *dev) /* reset vga */ vga_common_reset(&s->vga); s->mode =3D VGA_MODE; + s->host_data_pos =3D 0; } =20 static void ati_vga_exit(PCIDevice *dev) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 309bb5ccb6..6b0b4775ff 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -24,6 +24,9 @@ * possible. */ =20 +#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) +#define EXPANDED_SRC_BPP 32 + static int ati_bpp_from_datatype(ATIVGAState *s) { switch (s->regs.dp_datatype & 0xf) { @@ -43,7 +46,106 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) +/* Convert 1bpp monochrome data to 32bpp ARGB using color expansion */ +static void expand_colors(uint8_t *color_dst, const uint8_t *mono_src, + uint32_t width, uint32_t height, + uint32_t fg_color, uint32_t bg_color, + bool lsb_to_msb) +{ + uint32_t byte, color; + uint8_t *pixel; + int i, j, bit; + /* Rows are 32-bit aligned */ + int bytes_per_row =3D ((width + 31) / 32) * 4; + + for (i =3D 0; i < height; i++) { + for (j =3D 0; j < width; j++) { + byte =3D mono_src[i * bytes_per_row + (j / 8)]; + bit =3D lsb_to_msb ? 7 - (j % 8) : j % 8; + color =3D (byte >> bit) & 0x1 ? fg_color : bg_color; + pixel =3D &color_dst[(i * width + j) * 4]; + memcpy(pixel, &color, sizeof(color)); + } + } +} + +/* Blit color expanded HOST_DATA to the screen */ +static void ati_blt_mono_host_to_screen(ATIVGAState *s) +{ + DisplaySurface *ds =3D qemu_console_surface(s->vga.con); + + uint8_t *mono_data, *color_data, *dst_data; + uint32_t dst_stride, dst_x, dst_y, bpp; + uint32_t width =3D s->regs.dst_width; + uint32_t height =3D s->regs.dst_height; + uint32_t pixels =3D width * height; + bool lsb_to_msb =3D s->regs.dp_gui_master_cntl & GMC_BYTE_ORDER_LSB_TO= _MSB; + uint32_t fg_clr =3D s->regs.dp_src_frgd_clr; + uint32_t bg_clr =3D s->regs.dp_src_bkgd_clr; + + /* Monochrome source is 1 bpp aligned to 32-bit rows */ + uint32_t mono_size =3D ((width + 31) / 32) * 4 * height; + /* Color destination is 32 bpp */ + uint32_t clr_size =3D pixels * sizeof(uint32_t); + + if (s->host_data_pos < mono_size) { + qemu_log_mask(LOG_UNIMP, + "HOST_DATA blit requires %u bytes, buffer holds %u " + "(increase buffer size)\n", + mono_size, s->host_data_pos); + return; + } + + mono_data =3D s->host_data_buffer; + color_data =3D g_malloc(clr_size); + + expand_colors(color_data, mono_data, width, height, + fg_clr, bg_clr, lsb_to_msb); + + /* Rage 128 stores pitch as pixels * 8. We need pixels. */ + dst_stride =3D (DEFAULT_CNTL ? + s->regs.dst_pitch : s->regs.default_pitch) * 8; + dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? + s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); + dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? + s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); + bpp =3D ati_bpp_from_datatype(s); + dst_data =3D s->vga.vram_ptr + (DEFAULT_CNTL ? + s->regs.dst_offset : s->regs.default_offset); + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + dst_data +=3D s->regs.crtc_offset & 0x07ffffff; + } + /* And now we need stride in words to pass to pixman */ + dst_stride =3D (dst_stride * (bpp / 8)) / sizeof(uint32_t); + + pixman_blt((uint32_t *)color_data, (uint32_t *)dst_data, + width, dst_stride, EXPANDED_SRC_BPP, bpp, + 0, 0, dst_x, dst_y, + width, height); + DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", + color_data, dst_data, width, dst_stride, EXPANDED_SRC_BPP, bpp, + 0, 0, dst_x, dst_y, + width, height); + + g_free(color_data); + s->host_data_pos =3D 0; + + s->regs.dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? + dst_x + s->regs.dst_width : dst_x); + s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? + dst_y + s->regs.dst_height : dst_y); + + if (dst_data >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + dst_data < s->vga.vram_ptr + s->vga.vbe_start_addr + + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { + memory_region_set_dirty( + &s->vga.vram, s->vga.vbe_start_addr + + (DEFAULT_CNTL ? s->regs.dst_offset : s->regs.default_offse= t) + + dst_y * surface_stride(ds), + height * surface_stride(ds) + ); + } +} =20 void ati_2d_blt(ATIVGAState *s) { @@ -92,6 +194,12 @@ void ati_2d_blt(ATIVGAState *s) switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_SRCCOPY: { + uint32_t src =3D s->regs.dp_gui_master_cntl & GMC_SRC_SOURCE_MASK; + if (src =3D=3D GMC_SRC_SOURCE_HOST_DATA) { + ati_blt_mono_host_to_screen(s); + return; + } + bool fallback =3D false; unsigned src_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index 3ffa7f35df..5c799d540a 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -252,6 +252,15 @@ static struct ati_regdesc ati_reg_names[] =3D { {"MC_SRC1_CNTL", 0x19D8}, {"TEX_CNTL", 0x1800}, {"RAGE128_MPP_TB_CONFIG", 0x01c0}, + {"HOST_DATA0", 0x17c0}, + {"HOST_DATA1", 0x17c4}, + {"HOST_DATA2", 0x17c8}, + {"HOST_DATA3", 0x17cc}, + {"HOST_DATA4", 0x17d0}, + {"HOST_DATA5", 0x17d4}, + {"HOST_DATA6", 0x17d8}, + {"HOST_DATA7", 0x17dc}, + {"HOST_DATA_LAST", 0x17e0}, {NULL, -1} }; =20 diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index f5a47b82b0..7973ce99bf 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -14,6 +14,7 @@ #include "hw/i2c/bitbang_i2c.h" #include "vga_int.h" #include "qom/object.h" +#include "qemu/units.h" =20 /*#define DEBUG_ATI*/ =20 @@ -82,6 +83,9 @@ typedef struct ATIVGARegs { uint32_t default_pitch; uint32_t default_tile; uint32_t default_sc_bottom_right; + uint32_t sc_top_left; + uint32_t sc_bottom_right; + uint32_t src_sc_bottom_right; } ATIVGARegs; =20 struct ATIVGAState { @@ -100,6 +104,8 @@ struct ATIVGAState { MemoryRegion io; MemoryRegion mm; ATIVGARegs regs; + uint32_t host_data_pos; + uint8_t host_data_buffer[4 * MiB]; }; =20 const char *ati_reg_name(int num); diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index d7127748ff..4e9b4cc896 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -252,6 +252,15 @@ #define DP_T12_CNTL 0x178c #define DST_BRES_T1_LNTH 0x1790 #define DST_BRES_T2_LNTH 0x1794 +#define HOST_DATA0 0x17c0 +#define HOST_DATA1 0x17c4 +#define HOST_DATA2 0x17c8 +#define HOST_DATA3 0x17cc +#define HOST_DATA4 0x17d0 +#define HOST_DATA5 0x17d4 +#define HOST_DATA6 0x17d8 +#define HOST_DATA7 0x17dc +#define HOST_DATA_LAST 0x17e0 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 #define SCALE_OFFSET_0 0x1998 #define SCALE_PITCH 0x199c @@ -392,11 +401,10 @@ /* DP_GUI_MASTER_CNTL bit constants */ #define GMC_SRC_PITCH_OFFSET_CNTL 0x00000001 #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_DEFAULT 0x00000000 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_DP_SRC_RECT 0x02000000 #define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_AUX_CLIP_CLEAR 0x20000000 @@ -404,6 +412,22 @@ #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 =20 +/* DP_GUI_MASTER_CNTL DP_SRC_CLIPPING named constants */ +#define GMC_SRC_CLIPPING_MASK 0x00000004 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE_ALONE 0x00000004 + +/* DP_GUI_MASTER_CNTL DP_DST_CLIPPING named constants */ +#define GMC_DST_CLIPPING_MASK 0x00000008 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE_ALONE 0x00000008 + +/* DP_GUI_MASTER_CNTL DP_SRC_SOURCE named constants */ +#define GMC_SRC_SOURCE_MASK 0x07000000 +#define GMC_SRC_SOURCE_MEMORY 0x02000000 +#define GMC_SRC_SOURCE_HOST_DATA 0x03000000 +#define GMC_SRC_SOURCE_HOST_DATA_ALIGNED 0x04000000 + /* DP_GUI_MASTER_CNTL ROP3 named constants */ #define GMC_ROP3_MASK 0x00ff0000 #define ROP3_BLACKNESS 0x00000000 --=20 2.51.0