From nobody Wed Nov 5 03:05:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761712708; cv=none; d=zohomail.com; s=zohoarc; b=QJUNsPkEMmo0jv70ZaybBnEDEjRWI/CEobipa7h2nIunn1JftRu1s3QrwdSNTXBAcZmpCHK4xwLjiakWBLjtVd/fg1d/o1EfRinnenAIv+DXCRpJ95mrrcv+3drBxYYKzhZsP+c9lGv6VWdINfSHLTSmXfJO1CvYYbGosQ0f4sQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761712708; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Y9St8dY45B2iiAVao9q+Q2q7ndKJdZWXxR9PbzAGEy0=; b=JJrzYHCxkpsp2PxFTH3Y4ZOE91jFrXwvclJR4NWJHG2EaZcszNHBk0vpA+hFjMcfsuDZeS4PTCR6yOwao2a31PS86DXOiab5Mlp7FwaLsqBJeGmuGEOyWdHNm6Kx1boxybvLh2zYFJb5wcg+u8WyJiOvyb8u1jTREOqdcgmKnWw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761712708874301.9494550271394; Tue, 28 Oct 2025 21:38:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDxwL-00079B-P1; Wed, 29 Oct 2025 00:37:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxwJ-00077l-EV; Wed, 29 Oct 2025 00:37:39 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxwB-0004M3-7y; Wed, 29 Oct 2025 00:37:39 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 29 Oct 2025 12:37:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 29 Oct 2025 12:37:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file for maintainability Date: Wed, 29 Oct 2025 12:36:47 +0800 Message-ID: <20251029043710.1486573-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> References: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761712713234154100 This commit moves the Quanta-Q71L BMC machine implementation out of aspeed.c into a new standalone file aspeed_ast2400_quanta-q71l.c. This refactor continues the modularization effort for Aspeed platform support, placing each board=E2=80=99s logic in its own dedicated source fil= e. It improves maintainability, readability, and simplifies future development for new platforms without cluttering aspeed.c Key updates include: - Removed QUANTA_Q71L_BMC_HW_STRAP1 macro definition from aspeed.c. - Moved quanta_q71l_bmc_i2c_init() I=C2=B2C initialization logic into the n= ew file. - Moved aspeed_machine_quanta_q71l_class_init() and type registration. - Added aspeed_ast2400_quanta-q71l.c to the build system (meson.build). - Removed all Quanta-Q71L=E2=80=93specific code and macros from aspeed.c. No functional changes. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 66 ---------------------- hw/arm/aspeed_ast2400_quanta-q71l.c | 85 +++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 86 insertions(+), 66 deletions(-) create mode 100644 hw/arm/aspeed_ast2400_quanta-q71l.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 11c74c3e1b..3eb1d19373 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -70,19 +70,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) =20 -/* Quanta-Q71l hardware value */ -#define QUANTA_Q71L_BMC_HW_STRAP1 ( \ - SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ - SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=3D6, CWL=3D5 */)= | \ - SCU_AST2400_HW_STRAP_ACPI_DIS | \ - SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ - SCU_HW_STRAP_VGA_CLASS_CODE | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ - SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) = | \ - SCU_HW_STRAP_SPI_WIDTH | \ - SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ - SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) - /* AST2600 evb hardware value */ #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 @@ -362,38 +349,6 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *= bmc) object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_ab= ort); } =20 -static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - - /* - * The quanta-q71l platform expects tmp75s which are compatible with - * tmp105s. - */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4c); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4e); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4f); - - /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ - /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ - /* TODO: Add Memory Riser i2c mux and eeproms. */ - - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0= x74); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0= x77); - - /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ - - /* i2c-7 */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0= x70); - /* - i2c@0: pmbus@59 */ - /* - i2c@1: pmbus@58 */ - /* - i2c@2: pmbus@58 */ - /* - i2c@3: pmbus@59 */ - - /* TODO: i2c-7: Add PDB FRU eeprom@52 */ - /* TODO: i2c-8: Add BMC FRU eeprom@50 */ -} - static void ast2600_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1117,23 +1072,6 @@ static void aspeed_machine_palmetto_class_init(Objec= tClass *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Quanta-Q71l BMC (ARM926EJ-S)"; - amc->soc_name =3D "ast2400-a1"; - amc->hw_strap1 =3D QUANTA_Q71L_BMC_HW_STRAP1; - amc->fmc_model =3D "n25q256a"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 1; - amc->i2c_init =3D quanta_q71l_bmc_i2c_init; - mc->default_ram_size =3D 128 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, const void *data) { @@ -1517,10 +1455,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_qcom_firework_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("quanta-q71l-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_quanta_q71l_class_init, }, { .name =3D MACHINE_TYPE_NAME("rainier-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_qu= anta-q71l.c new file mode 100644 index 0000000000..cda0406ace --- /dev/null +++ b/hw/arm/aspeed_ast2400_quanta-q71l.c @@ -0,0 +1,85 @@ +/* + * Quanta Q71l + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" + +/* Quanta-Q71l hardware value */ +#define QUANTA_Q71L_BMC_HW_STRAP1 ( \ + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=3D6, CWL=3D5 */)= | \ + SCU_AST2400_HW_STRAP_ACPI_DIS | \ + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) = | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) + +static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + /* + * The quanta-q71l platform expects tmp75s which are compatible with + * tmp105s. + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4e); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x= 4f); + + /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ + /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ + /* TODO: Add Memory Riser i2c mux and eeproms. */ + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0= x74); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0= x77); + + /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ + + /* i2c-7 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0= x70); + /* - i2c@0: pmbus@59 */ + /* - i2c@1: pmbus@58 */ + /* - i2c@2: pmbus@58 */ + /* - i2c@3: pmbus@59 */ + + /* TODO: i2c-7: Add PDB FRU eeprom@52 */ + /* TODO: i2c-8: Add BMC FRU eeprom@50 */ +} + +static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Quanta-Q71l BMC (ARM926EJ-S)"; + amc->soc_name =3D "ast2400-a1"; + amc->hw_strap1 =3D QUANTA_Q71L_BMC_HW_STRAP1; + amc->fmc_model =3D "n25q256a"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 1; + amc->i2c_init =3D quanta_q71l_bmc_i2c_init; + mc->default_ram_size =3D 128 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast2400_quanta_q71l_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("quanta-q71l-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_quanta_q71l_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2400_quanta_q71l_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index cbee7ebf60..4475807e11 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', + 'aspeed_ast2400_quanta-q71l.c', 'aspeed_ast2500_evb.c', 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', --=20 2.43.0