From nobody Wed Nov 5 02:39:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761712825; cv=none; d=zohomail.com; s=zohoarc; b=f14tXpigd9m9n07PA6pNqykOMvtk7QbAWow+oQsvUKfoovmeTHsCP8p6XlRcgqFMdBVIJxeuvXkmf553nMAKBlw8iF+igHZ+cN9AKvg6OVcxEjom7RVJx4svjIYegY5HL6RxrwN/Y0KbPuRS6JzVhz85K2WhYXHY4dFs1tvJgtE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761712825; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=eHESCrHSkaE4xNmgmAnps/joR72JRFrl0oDjHmBr1m0=; b=OX8hzTLsTqMwr5fz9TBgxYF6lOdttnWRiFeM+yGFO+KiFPE8/TUm3PaI93QjigsMARtDB+b9ivbuj9h1NIblFSsyeyd/toZy2gDQCPCi4H6/E9vLPw5RjHb4ESImzA4djMeRWtbk2aTbrtBvpxGJuQ35F7DxIfpLnylVwHAxyKw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761712825418927.5197019506516; Tue, 28 Oct 2025 21:40:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDxxl-0000dW-Df; Wed, 29 Oct 2025 00:39:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxxi-0000b0-PW; Wed, 29 Oct 2025 00:39:06 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxxd-0004Ya-86; Wed, 29 Oct 2025 00:39:04 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 29 Oct 2025 12:37:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 29 Oct 2025 12:37:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v2 11/17] hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability Date: Wed, 29 Oct 2025 12:36:57 +0800 Message-ID: <20251029043710.1486573-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> References: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761712827768154100 This commit moves the Nvidia GB200NVL BMC machine implementation out of aspeed.c into a new standalone file aspeed_ast2600_gb200nvl.c. This refactor continues the modularization effort for Aspeed platform suppo= rt, placing each board=E2=80=99s initialization logic in its own dedicated sour= ce file. It improves code maintainability, readability, and simplifies adding new platforms without increasing the complexity of aspeed.c. Key updates include: - Moved GB200NVL_BMC_HW_STRAP1 and GB200NVL_BMC_HW_STRAP2 macro definitions= into the new file. - Moved gb200nvl_bmc_i2c_init() and its related FRUID setup into the new fi= le. - Moved aspeed_machine_gb200nvl_class_init() and type registration logic ou= t of aspeed.c. - Removed gb200nvl_bmc_fruid[] and its length definition from aspeed_eeprom= .c/h. - Added aspeed_ast2600_gb200nvl.c to the Meson build system (meson.build). - Cleaned up all GB200NVL-specific code and data from aspeed.c and aspeed_e= eprom.c. No functional changes. Signed-off-by: Jamin Lin --- hw/arm/aspeed_eeprom.h | 3 - hw/arm/aspeed.c | 71 -------------------- hw/arm/aspeed_ast2600_gb200nvl.c | 110 +++++++++++++++++++++++++++++++ hw/arm/aspeed_eeprom.c | 20 ------ hw/arm/meson.build | 1 + 5 files changed, 111 insertions(+), 94 deletions(-) create mode 100644 hw/arm/aspeed_ast2600_gb200nvl.c diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index 7207bb2cbd..86b97e4c6d 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -12,7 +12,4 @@ extern const size_t rainier_bb_fruid_len; extern const uint8_t rainier_bmc_fruid[]; extern const size_t rainier_bmc_fruid_len; =20 -extern const uint8_t gb200nvl_bmc_fruid[]; -extern const size_t gb200nvl_bmc_fruid_len; - #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 8a6a5b3e91..f508280050 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -51,10 +51,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_= EMMC) #define RAINIER_BMC_HW_STRAP2 0x80000848 =20 -/* GB200NVL hardware value */ -#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 -#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 - #define AST_SMP_MAILBOX_BASE 0x1e6e2180 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) @@ -585,44 +581,6 @@ static void catalina_bmc_i2c_init(AspeedMachineState *= bmc) at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); } =20 -static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - I2CBus *i2c[15] =3D {}; - DeviceState *dev; - for (int i =3D 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) { - if ((i =3D=3D 11) || (i =3D=3D 12) || (i =3D=3D 13)) { - continue; - } - i2c[i] =3D aspeed_i2c_get_bus(&soc->i2c, i); - } - - /* Bus 5 Expander */ - create_pca9554(soc, 4, 0x21); - - /* Mux I2c Expanders */ - i2c_slave_create_simple(i2c[5], "pca9546", 0x71); - i2c_slave_create_simple(i2c[5], "pca9546", 0x72); - i2c_slave_create_simple(i2c[5], "pca9546", 0x73); - i2c_slave_create_simple(i2c[5], "pca9546", 0x75); - i2c_slave_create_simple(i2c[5], "pca9546", 0x76); - i2c_slave_create_simple(i2c[5], "pca9546", 0x77); - - /* Bus 10 */ - dev =3D DEVICE(create_pca9554(soc, 9, 0x20)); - - /* Set FPGA_READY */ - object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal); - - create_pca9554(soc, 9, 0x21); - at24c_eeprom_init(i2c[9], 0x50, 64 * KiB); - at24c_eeprom_init(i2c[9], 0x51, 64 * KiB); - - /* Bus 11 */ - at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid, - gb200nvl_bmc_fruid_len); -} - static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -840,31 +798,6 @@ static void aspeed_machine_catalina_class_init(ObjectC= lass *oc, aspeed_machine_ast2600_class_emmc_init(oc); } =20 -#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB) - -static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Nvidia GB200NVL BMC (Cortex-A7)"; - amc->soc_name =3D "ast2600-a3"; - amc->hw_strap1 =3D GB200NVL_BMC_HW_STRAP1; - amc->hw_strap2 =3D GB200NVL_BMC_HW_STRAP2; - amc->fmc_model =3D "mx66u51235f"; - amc->spi_model =3D "mx66u51235f"; - amc->num_cs =3D 2; - - amc->spi2_model =3D "mx66u51235f"; - amc->num_cs2 =3D 1; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init =3D gb200nvl_bmc_i2c_init; - mc->default_ram_size =3D GB200NVL_BMC_RAM_SIZE; - aspeed_machine_class_init_cpus_defaults(mc); - aspeed_machine_ast2600_class_emmc_init(oc); -} - #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) /* Main SYSCLK frequency in Hz (200MHz) */ #define SYSCLK_FRQ 200000000ULL @@ -1008,10 +941,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("rainier-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_rainier_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("gb200nvl-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_gb200nvl_class_init, }, { .name =3D MACHINE_TYPE_NAME("catalina-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200= nvl.c new file mode 100644 index 0000000000..4ecf7e6c00 --- /dev/null +++ b/hw/arm/aspeed_ast2600_gb200nvl.c @@ -0,0 +1,110 @@ +/* + * Nvidia GB200NVL + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" + +/* GB200NVL hardware value */ +#define GB200NVL_BMC_HW_STRAP1 0x000000C0 +#define GB200NVL_BMC_HW_STRAP2 0x00000003 +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB) + +static const uint8_t gb200nvl_bmc_fruid[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f, + 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33, + 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, + 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, + 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, + 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a, + 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a, + 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44, + 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43, + 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30, + 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31, + 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31, + 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + +}; +static const size_t gb200nvl_bmc_fruid_len =3D sizeof(gb200nvl_bmc_fruid); + +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + I2CBus *i2c[15] =3D {}; + DeviceState *dev; + for (int i =3D 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) { + if ((i =3D=3D 11) || (i =3D=3D 12) || (i =3D=3D 13)) { + continue; + } + i2c[i] =3D aspeed_i2c_get_bus(&soc->i2c, i); + } + + /* Bus 5 Expander */ + create_pca9554(soc, 4, 0x21); + + /* Mux I2c Expanders */ + i2c_slave_create_simple(i2c[5], "pca9546", 0x71); + i2c_slave_create_simple(i2c[5], "pca9546", 0x72); + i2c_slave_create_simple(i2c[5], "pca9546", 0x73); + i2c_slave_create_simple(i2c[5], "pca9546", 0x75); + i2c_slave_create_simple(i2c[5], "pca9546", 0x76); + i2c_slave_create_simple(i2c[5], "pca9546", 0x77); + + /* Bus 10 */ + dev =3D DEVICE(create_pca9554(soc, 9, 0x20)); + + /* Set FPGA_READY */ + object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal); + + create_pca9554(soc, 9, 0x21); + at24c_eeprom_init(i2c[9], 0x50, 64 * KiB); + at24c_eeprom_init(i2c[9], 0x51, 64 * KiB); + + /* Bus 11 */ + at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid, + gb200nvl_bmc_fruid_len); +} + +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Nvidia GB200NVL BMC (Cortex-A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D GB200NVL_BMC_HW_STRAP1; + amc->hw_strap2 =3D GB200NVL_BMC_HW_STRAP2; + amc->fmc_model =3D "mx66u51235f"; + amc->spi_model =3D "mx66u51235f"; + amc->num_cs =3D 2; + + amc->spi2_model =3D "mx66u51235f"; + amc->num_cs2 =3D 1; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init =3D gb200nvl_bmc_i2c_init; + mc->default_ram_size =3D GB200NVL_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast2600_class_emmc_init(oc); +} + +static const TypeInfo aspeed_ast2600_gb200nvl_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("gb200nvl-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_gb200nvl_class_init, + }, +}; + +DEFINE_TYPES(aspeed_ast2600_gb200nvl_types) + diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index 53c9b0d56f..85a2aa4036 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -49,26 +49,6 @@ const uint8_t rainier_bmc_fruid[] =3D { 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, }; =20 -const uint8_t gb200nvl_bmc_fruid[] =3D { - 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f, - 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33, - 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, - 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, - 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, - 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a, - 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a, - 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44, - 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43, - 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30, - 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31, - 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31, - 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - -}; - const size_t rainier_bb_fruid_len =3D sizeof(rainier_bb_fruid); const size_t rainier_bmc_fruid_len =3D sizeof(rainier_bmc_fruid); -const size_t gb200nvl_bmc_fruid_len =3D sizeof(gb200nvl_bmc_fruid); =20 diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 2813698918..5f6036fdb0 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -60,6 +60,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2600_bletchley.c', 'aspeed_ast2600_fby35.c', 'aspeed_ast2600_fuji.c', + 'aspeed_ast2600_gb200nvl.c', 'aspeed_ast2600_qcom-dc-scm-v1.c', 'aspeed_ast2600_qcom-firework.c', 'aspeed_ast10x0.c', --=20 2.43.0