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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=n.novikov@syntacore.com; helo=m.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1761722316812158500 According to the RISC-V AIA v1.0, section 4.5.2 ("Source configurations"), register target[i] shall be read-only zero when interrupt source i is inact= ive in this domain. A source is inactive if it is delegated to a child domain or its source mode is INACTIVE. The previous implementation only checked SM =3D=3D INACTIVE. This patch adds full compliance: - Return zero on read if D =3D=3D 1 or SM =3D=3D INACTIVE - Ignore writes in both cases Fixes: b6f1244678 ("intc/riscv_aplic: Fix target register read when source = is inactive") Signed-off-by: Nikita Novikov Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index a2041e702245211ba3bcf4334301d7c86272e36f..8c3b16074cd3ca1bc3004cfaaa1= 3f34b8860bd48 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -193,6 +193,26 @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *a= plic, hwaddr addr) #endif } =20 +/* + * APLIC target[i] must be read-only zero if the source i is inactive + * in this domain (delegated or SM =3D=3D INACTIVE) + */ +static inline bool riscv_aplic_source_active(RISCVAPLICState *aplic, + uint32_t irq) +{ + uint32_t sc, sm; + + if ((irq =3D=3D 0) || (aplic->num_irqs <=3D irq)) { + return false; + } + sc =3D aplic->sourcecfg[irq]; + if (sc & APLIC_SOURCECFG_D) { + return false; + } + sm =3D sc & APLIC_SOURCECFG_SM_MASK; + return sm !=3D APLIC_SOURCECFG_SM_INACTIVE; +} + static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { @@ -635,7 +655,7 @@ static void riscv_aplic_request(void *opaque, int irq, = int level) =20 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) { - uint32_t irq, word, idc, sm; + uint32_t irq, word, idc; RISCVAPLICState *aplic =3D opaque; =20 /* Reads must be 4 byte words */ @@ -703,8 +723,7 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr a= ddr, unsigned size) } else if ((APLIC_TARGET_BASE <=3D addr) && (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; - sm =3D aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; - if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + if (!riscv_aplic_source_active(aplic, irq)) { return 0; } return aplic->target[irq]; @@ -841,6 +860,9 @@ static void riscv_aplic_write(void *opaque, hwaddr addr= , uint64_t value, } else if ((APLIC_TARGET_BASE <=3D addr) && (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; + if (!riscv_aplic_source_active(aplic, irq)) { + return; + } if (aplic->msimode) { aplic->target[irq] =3D value; } else { --=20 2.51.0