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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.188; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695605223154100 Content-Type: text/plain; charset="utf-8" From: Sebastian Ott Add constants for PSCI version 1_2 and 1_3. Signed-off-by: Sebastian Ott Reviewed-by: Pierrick Bouvier --- target/arm/kvm-consts.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 54ae5da7ce..9fba3e886d 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -97,6 +97,8 @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_F= N_PSCI_FEATURES); #define QEMU_PSCI_VERSION_0_2 0x00002 #define QEMU_PSCI_VERSION_1_0 0x10000 #define QEMU_PSCI_VERSION_1_1 0x10001 +#define QEMU_PSCI_VERSION_1_2 0x10002 +#define QEMU_PSCI_VERSION_1_3 0x10003 =20 MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_= MP); /* We don't bother to check every possible version value */ --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.193; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695731650158500 From: Philippe Mathieu-Daud=C3=A9 hwaccel_enabled() return whether any hardware accelerator is enabled. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/system/hw_accel.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h index 55497edc29..628a50e066 100644 --- a/include/system/hw_accel.h +++ b/include/system/hw_accel.h @@ -40,4 +40,17 @@ void cpu_synchronize_pre_loadvm(CPUState *cpu); void cpu_synchronize_post_reset(CPUState *cpu); void cpu_synchronize_post_init(CPUState *cpu); =20 +/** + * hwaccel_enabled: + * + * Returns: %true if a hardware accelerator is enabled, %false otherwise. + */ +static inline bool hwaccel_enabled(void) +{ + return hvf_enabled() + || kvm_enabled() + || nvmm_enabled() + || whpx_enabled(); +} + #endif /* QEMU_HW_ACCEL_H */ --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" On Hypervisor.framework for macOS and WHPX for Windows, the provided enviro= nment is a GICv3 without ITS. As such, support a GICv3 w/ GICv2m for that scenario. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 8bb6b60515..0a6ec74aa0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -959,7 +959,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) && !vms->n= o_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 175023897a..61d7bab803 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -956,6 +956,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); + } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { + create_v2m(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); } @@ -2447,6 +2449,8 @@ static void machvirt_init(MachineState *machine) vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && !vmc->no_ns_el2_virt_timer_irq; =20 + vms->no_gicv3_with_gicv2m =3D vmc->no_gicv3_with_gicv2m; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3484,6 +3488,7 @@ static void virt_instance_init(Object *obj) vms->its =3D true; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; + vms->no_gicv3_with_gicv2m =3D false; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; @@ -3536,9 +3541,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 2) =20 static void virt_machine_10_1_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_10_2_options(mc); mc->smbios_memory_device_size =3D 2047 * TiB; compat_props_add(mc->compat_props, hw_compat_10_1, hw_compat_10_1_len); + vmc->no_gicv3_with_gicv2m =3D true; } DEFINE_VIRT_MACHINE(10, 1) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 04a09af354..d31348dd61 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -132,6 +132,7 @@ struct VirtMachineClass { bool no_cpu_topology; bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; bool no_nested_smmu; }; =20 @@ -180,6 +181,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; CXLState cxl_devices_state; bool legacy_smmuv3_present; }; --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.173; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695712367154100 Content-Type: text/plain; charset="utf-8" After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI table for the its=3Doff case. Signed-off-by: Mohamed Mediouni --- tests/data/acpi/aarch64/virt/APIC.its_off | Bin 164 -> 188 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aa= rch64/virt/APIC.its_off index 6130cb7d07103b326feb4dcd7034f85808bebadf..16a01a17c0af605daf64f3cd2de= 3572be9e60cab 100644 GIT binary patch delta 43 qcmZ3&xQCI;F~HM#4+8@Oi@`*$SrWVwKqeS4aeydBAa-B~U;qHCpaq8j delta 18 ZcmdnPxP+0*F~HM#2?GNI3&%vRSpY3v1aANU diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index bfc4d60124..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.202; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695422940158500 Switch to a design where we can share whpx code between x86 and AArch64 whe= n it makes sense to do so. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 2 ++ accel/meson.build | 1 + accel/whpx/meson.build | 6 ++++++ {target/i386 =3D> accel}/whpx/whpx-accel-ops.c | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-accel-ops.h | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-internal.h | 5 +++-- target/i386/whpx/meson.build | 1 - target/i386/whpx/whpx-all.c | 4 ++-- target/i386/whpx/whpx-apic.c | 2 +- 9 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 accel/whpx/meson.build rename {target/i386 =3D> accel}/whpx/whpx-accel-ops.c (97%) rename {target/i386/whpx =3D> include/system}/whpx-accel-ops.h (92%) rename {target/i386/whpx =3D> include/system}/whpx-internal.h (98%) diff --git a/MAINTAINERS b/MAINTAINERS index 64491c800c..4ea4c48a2a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -549,9 +549,11 @@ F: include/system/hvf_int.h WHPX CPUs M: Sunil Muthuswamy S: Supported +F: accel/whpx/ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h +F: include/system/whpx-accel-ops.h =20 MSHV M: Magnus Kulke diff --git a/accel/meson.build b/accel/meson.build index 983dfd0bd5..289b7420ff 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -6,6 +6,7 @@ user_ss.add(files('accel-user.c')) subdir('tcg') if have_system subdir('hvf') + subdir('whpx') subdir('qtest') subdir('kvm') subdir('xen') diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build new file mode 100644 index 0000000000..7b3d6f1c1c --- /dev/null +++ b/accel/whpx/meson.build @@ -0,0 +1,6 @@ +whpx_ss =3D ss.source_set() +whpx_ss.add(files( + 'whpx-accel-ops.c', +)) + +specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/target/i386/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c similarity index 97% rename from target/i386/whpx/whpx-accel-ops.c rename to accel/whpx/whpx-accel-ops.c index f75886128d..c84a25c273 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -16,8 +16,8 @@ #include "qemu/guest-random.h" =20 #include "system/whpx.h" -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 static void *whpx_cpu_thread_fn(void *arg) { diff --git a/target/i386/whpx/whpx-accel-ops.h b/include/system/whpx-accel-= ops.h similarity index 92% rename from target/i386/whpx/whpx-accel-ops.h rename to include/system/whpx-accel-ops.h index 54cfc25a14..ed9d4c49f4 100644 --- a/target/i386/whpx/whpx-accel-ops.h +++ b/include/system/whpx-accel-ops.h @@ -7,8 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef TARGET_I386_WHPX_ACCEL_OPS_H -#define TARGET_I386_WHPX_ACCEL_OPS_H +#ifndef SYSTEM_WHPX_ACCEL_OPS_H +#define SYSTEM_WHPX_ACCEL_OPS_H =20 #include "system/cpus.h" =20 diff --git a/target/i386/whpx/whpx-internal.h b/include/system/whpx-interna= l.h similarity index 98% rename from target/i386/whpx/whpx-internal.h rename to include/system/whpx-internal.h index 2dcad1f565..c59f9de091 100644 --- a/target/i386/whpx/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -1,5 +1,6 @@ -#ifndef TARGET_I386_WHPX_INTERNAL_H -#define TARGET_I386_WHPX_INTERNAL_H +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_INTERNAL_H +#define SYSTEM_WHPX_INTERNAL_H =20 #include #include diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index 9c54aaad39..c3aaaff9fd 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,5 +1,4 @@ i386_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-apic.c', - 'whpx-accel-ops.c', )) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 256761834c..106a352980 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -31,8 +31,8 @@ #include "accel/accel-cpu-target.h" #include =20 -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 #include #include diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index afcb25843b..b934fdcbe1 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -18,7 +18,7 @@ #include "hw/pci/msi.h" #include "system/hw_accel.h" #include "system/whpx.h" -#include "whpx-internal.h" +#include "system/whpx-internal.h" =20 struct whpx_lapic_state { struct { --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Some code can be shared between x86_64 and arm64 WHPX. Do so as much as rea= sonable. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 2 + accel/whpx/meson.build | 1 + accel/whpx/whpx-common.c | 562 +++++++++++++++++++++++++++++++++++ include/system/whpx-all.h | 20 ++ include/system/whpx-common.h | 21 ++ target/i386/whpx/whpx-all.c | 551 +--------------------------------- 6 files changed, 616 insertions(+), 541 deletions(-) create mode 100644 accel/whpx/whpx-common.c create mode 100644 include/system/whpx-all.h create mode 100644 include/system/whpx-common.h diff --git a/MAINTAINERS b/MAINTAINERS index 4ea4c48a2a..c6b7f45459 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -554,6 +554,8 @@ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h +F: include/system/whpx-common.h +F: include/system/whpx-internal.h =20 MSHV M: Magnus Kulke diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build index 7b3d6f1c1c..fad28dddcb 100644 --- a/accel/whpx/meson.build +++ b/accel/whpx/meson.build @@ -1,6 +1,7 @@ whpx_ss =3D ss.source_set() whpx_ss.add(files( 'whpx-accel-ops.c', + 'whpx-common.c' )) =20 specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c new file mode 100644 index 0000000000..66c9238586 --- /dev/null +++ b/accel/whpx/whpx-common.c @@ -0,0 +1,562 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright Microsoft Corp. 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/boards.h" +#include "hw/intc/ioapic.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-common.h" +#include "system/whpx-all.h" + +#include +#include + +bool whpx_allowed; +static bool whp_dispatch_initialized; +static HMODULE hWinHvPlatform; +static HMODULE hWinHvEmulation; + +struct whpx_state whpx_global; +struct WHPDispatch whp_dispatch; + +/* Tries to find a breakpoint at the specified address. */ +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address) +{ + struct whpx_state *whpx =3D &whpx_global; + int i; + + if (whpx->breakpoints.breakpoints) { + for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { + if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { + return &whpx->breakpoints.breakpoints->data[i]; + } + } + } + + return NULL; +} + +/* + * This function is called when the a VCPU is about to start and no other + * VCPUs have been started so far. Since the VCPU start order could be + * arbitrary, it doesn't have to be VCPU#0. + * + * It is used to commit the breakpoints into memory, and configure WHPX + * to intercept debug exceptions. + * + * Note that whpx_set_exception_exit_bitmap() cannot be called if one or + * more VCPUs are already running, so this is the best place to do it. + */ +int whpx_first_vcpu_starting(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + g_assert(bql_locked()); + + if (!QTAILQ_EMPTY(&cpu->breakpoints) || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + CPUBreakpoint *bp; + int i =3D 0; + bool update_pending =3D false; + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (i >=3D whpx->breakpoints.original_address_count || + bp->pc !=3D whpx->breakpoints.original_addresses[i]) { + update_pending =3D true; + } + + i++; + } + + if (i !=3D whpx->breakpoints.original_address_count) { + update_pending =3D true; + } + + if (update_pending) { + /* + * The CPU breakpoints have changed since the last call to + * whpx_translate_cpu_breakpoints(). WHPX breakpoints must + * now be recomputed. + */ + whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); + } + /* Actually insert the breakpoints into the memory. */ + whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); + } + HRESULT hr; + uint64_t exception_mask; + if (whpx->step_pending || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + /* + * We are either attempting to single-step one or more CPUs, or + * have one or more breakpoints enabled. Both require intercepting + * the WHvX64ExceptionTypeBreakpointTrap exception. + */ + exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + } else { + /* Let the guest handle all exceptions. */ + exception_mask =3D 0; + } + hr =3D whpx_set_exception_exit_bitmap(exception_mask); + if (!SUCCEEDED(hr)) { + error_report("WHPX: Failed to update exception exit mask," + "hr=3D%08lx.", hr); + return 1; + } + return 0; +} + +/* + * This function is called when the last VCPU has finished running. + * It is used to remove any previously set breakpoints from memory. + */ +int whpx_last_vcpu_stopping(CPUState *cpu) +{ + whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); + return 0; +} + +static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) +{ + if (!cpu->vcpu_dirty) { + whpx_get_registers(cpu); + cpu->vcpu_dirty =3D true; + } +} + +static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_RESET_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_FULL_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, + run_on_cpu_data arg) +{ + cpu->vcpu_dirty =3D true; +} + +/* + * CPU support. + */ + +void whpx_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +void whpx_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +static void whpx_pre_resume_vm(AccelState *as, bool step_pending) +{ + whpx_global.step_pending =3D step_pending; +} + +/* + * Vcpu support. + */ + +int whpx_vcpu_exec(CPUState *cpu) +{ + int ret; + int fatal; + + for (;;) { + if (cpu->exception_index >=3D EXCP_INTERRUPT) { + ret =3D cpu->exception_index; + cpu->exception_index =3D -1; + break; + } + + fatal =3D whpx_vcpu_run(cpu); + + if (fatal) { + error_report("WHPX: Failed to exec a virtual processor"); + abort(); + } + } + + return ret; +} + +void whpx_destroy_vcpu(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); + AccelCPUState *vcpu =3D cpu->accel; + whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); + g_free(cpu->accel); +} + + +void whpx_vcpu_kick(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + whp_dispatch.WHvCancelRunVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); +} + +/* + * Memory support. + */ + +static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, + void *host_va, int add, int rom, + const char *name) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + /* + if (add) { + printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", + (void*)start_pa, (void*)size, host_va, + (rom ? "ROM" : "RAM"), name); + } else { + printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", + (void*)start_pa, (void*)size, host_va, name); + } + */ + + if (add) { + hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + host_va, + start_pa, + size, + (WHvMapGpaRangeFlagRead | + WHvMapGpaRangeFlagExecute | + (rom ? 0 : WHvMapGpaRangeFlagWri= te))); + } else { + hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, + start_pa, + size); + } + + if (FAILED(hr)) { + error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," + " Host:%p, hr=3D%08lx", + (add ? "MAP" : "UNMAP"), name, + (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + } +} + +static void whpx_process_section(MemoryRegionSection *section, int add) +{ + MemoryRegion *mr =3D section->mr; + hwaddr start_pa =3D section->offset_within_address_space; + ram_addr_t size =3D int128_get64(section->size); + unsigned int delta; + uint64_t host_va; + + if (!memory_region_is_ram(mr)) { + return; + } + + delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); + delta &=3D ~qemu_real_host_page_mask(); + if (delta > size) { + return; + } + start_pa +=3D delta; + size -=3D delta; + size &=3D qemu_real_host_page_mask(); + if (!size || (start_pa & ~qemu_real_host_page_mask())) { + return; + } + + host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) + + section->offset_within_region + delta; + + whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, + memory_region_is_rom(mr), mr->name); +} + +static void whpx_region_add(MemoryListener *listener, + MemoryRegionSection *section) +{ + memory_region_ref(section->mr); + whpx_process_section(section, 1); +} + +static void whpx_region_del(MemoryListener *listener, + MemoryRegionSection *section) +{ + whpx_process_section(section, 0); + memory_region_unref(section->mr); +} + +static void whpx_transaction_begin(MemoryListener *listener) +{ +} + +static void whpx_transaction_commit(MemoryListener *listener) +{ +} + +static void whpx_log_sync(MemoryListener *listener, + MemoryRegionSection *section) +{ + MemoryRegion *mr =3D section->mr; + + if (!memory_region_is_ram(mr)) { + return; + } + + memory_region_set_dirty(mr, 0, int128_get64(section->size)); +} + +static MemoryListener whpx_memory_listener =3D { + .name =3D "whpx", + .begin =3D whpx_transaction_begin, + .commit =3D whpx_transaction_commit, + .region_add =3D whpx_region_add, + .region_del =3D whpx_region_del, + .log_sync =3D whpx_log_sync, + .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, +}; + +void whpx_memory_init(void) +{ + memory_listener_register(&whpx_memory_listener, &address_space_memory); +} + +/* + * Load the functions from the given library, using the given handle. If a + * handle is provided, it is used, otherwise the library is opened. The + * handle will be updated on return with the opened one. + */ +static bool load_whp_dispatch_fns(HMODULE *handle, + WHPFunctionList function_list) +{ + HMODULE hLib =3D *handle; + + #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" + #define WINHV_EMULATION_DLL "WinHvEmulation.dll" + #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + + #define WHP_LOAD_FIELD(return_type, function_name, signature) \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + if (!whp_dispatch.function_name) { \ + error_report("Could not load function %s", #function_name); \ + goto error; \ + } \ + + #define WHP_LOAD_LIB(lib_name, handle_lib) \ + if (!handle_lib) { \ + handle_lib =3D LoadLibrary(lib_name); \ + if (!handle_lib) { \ + error_report("Could not load library %s.", lib_name); \ + goto error; \ + } \ + } \ + + switch (function_list) { + case WINHV_PLATFORM_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_EMULATION_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) + LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_PLATFORM_FNS_SUPPLEMENTAL: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) + break; + } + + *handle =3D hLib; + return true; + +error: + if (hLib) { + FreeLibrary(hLib); + } + + return false; +} + +static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + struct whpx_state *whpx =3D &whpx_global; + OnOffSplit mode; + + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + whpx->kernel_irqchip_allowed =3D true; + whpx->kernel_irqchip_required =3D true; + break; + + case ON_OFF_SPLIT_OFF: + whpx->kernel_irqchip_allowed =3D false; + whpx->kernel_irqchip_required =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "WHPX: split irqchip currently not supported"); + error_append_hint(errp, + "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +} + +static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D whpx_cpu_instance_init; +} + +static const TypeInfo whpx_cpu_accel_type =3D { + .name =3D ACCEL_CPU_NAME("whpx"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D whpx_cpu_accel_class_init, + .abstract =3D true, +}; + +/* + * Partition support + */ + +bool whpx_apic_in_platform(void) +{ + return whpx_global.apic_in_platform; +} + +static void whpx_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelClass *ac =3D ACCEL_CLASS(oc); + ac->name =3D "WHPX"; + ac->init_machine =3D whpx_accel_init; + ac->pre_resume_vm =3D whpx_pre_resume_vm; + ac->allowed =3D &whpx_allowed; + + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, whpx_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure WHPX in-kernel irqchip"); +} + +static void whpx_accel_instance_init(Object *obj) +{ + struct whpx_state *whpx =3D &whpx_global; + + memset(whpx, 0, sizeof(struct whpx_state)); + /* Turn on kernel-irqchip, by default */ + whpx->kernel_irqchip_allowed =3D true; +} + +static const TypeInfo whpx_accel_type =3D { + .name =3D ACCEL_CLASS_NAME("whpx"), + .parent =3D TYPE_ACCEL, + .instance_init =3D whpx_accel_instance_init, + .class_init =3D whpx_accel_class_init, +}; + +static void whpx_type_init(void) +{ + type_register_static(&whpx_accel_type); + type_register_static(&whpx_cpu_accel_type); +} + +bool init_whp_dispatch(void) +{ + if (whp_dispatch_initialized) { + return true; + } + + if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { + goto error; + } + + if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { + goto error; + } + + assert(load_whp_dispatch_fns(&hWinHvPlatform, + WINHV_PLATFORM_FNS_SUPPLEMENTAL)); + whp_dispatch_initialized =3D true; + + return true; +error: + if (hWinHvPlatform) { + FreeLibrary(hWinHvPlatform); + } + if (hWinHvEmulation) { + FreeLibrary(hWinHvEmulation); + } + return false; +} + +type_init(whpx_type_init); diff --git a/include/system/whpx-all.h b/include/system/whpx-all.h new file mode 100644 index 0000000000..f13cdf7f66 --- /dev/null +++ b/include/system/whpx-all.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_ALL_H +#define SYSTEM_WHPX_ALL_H + +/* Called by whpx-common */ +int whpx_vcpu_run(CPUState *cpu); +void whpx_get_registers(CPUState *cpu); +void whpx_set_registers(CPUState *cpu, int level); +int whpx_accel_init(AccelState *as, MachineState *ms); +void whpx_cpu_instance_init(CPUState *cs); +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions); +void whpx_apply_breakpoints( +struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming); +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count); +#endif diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h new file mode 100644 index 0000000000..e549c7539c --- /dev/null +++ b/include/system/whpx-common.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_COMMON_H +#define SYSTEM_WHPX_COMMON_H + +struct AccelCPUState { + WHV_EMULATOR_HANDLE emulator; + bool window_registered; + bool interruptable; + bool ready_for_pic_interrupt; + uint64_t tpr; + uint64_t apic_base; + bool interruption_pending; + /* Must be the last field as it may have a tail */ + WHV_RUN_VP_EXIT_CONTEXT exit_ctx; +}; + +int whpx_first_vcpu_starting(CPUState *cpu); +int whpx_last_vcpu_stopping(CPUState *cpu); +void whpx_memory_init(void); +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); +#endif diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 106a352980..d1f8e49cb2 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -33,6 +33,8 @@ =20 #include "system/whpx-internal.h" #include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" =20 #include #include @@ -232,28 +234,9 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct AccelCPUState { - WHV_EMULATOR_HANDLE emulator; - bool window_registered; - bool interruptable; - bool ready_for_pic_interrupt; - uint64_t tpr; - uint64_t apic_base; - bool interruption_pending; - - /* Must be the last field as it may have a tail */ - WHV_RUN_VP_EXIT_CONTEXT exit_ctx; -}; - -bool whpx_allowed; -static bool whp_dispatch_initialized; -static HMODULE hWinHvPlatform, hWinHvEmulation; static uint32_t max_vcpu_index; static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap; =20 -struct whpx_state whpx_global; -struct WHPDispatch whp_dispatch; - static bool whpx_has_xsave(void) { return whpx_xsave_cap.XsaveSupport; @@ -379,7 +362,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) return cr8 << 4; } =20 -static void whpx_set_registers(CPUState *cpu, int level) +void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -594,7 +577,7 @@ static void whpx_get_xcrs(CPUState *cpu) cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 -static void whpx_get_registers(CPUState *cpu) +void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -934,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, * The 'exceptions' argument accepts a bitmask, e.g: * (1 << WHvX64ExceptionTypeDebugTrapOrFault) | (...) */ -static HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) { struct whpx_state *whpx =3D &whpx_global; WHV_PARTITION_PROPERTY prop =3D { 0, }; @@ -1084,23 +1067,6 @@ static HRESULT whpx_vcpu_configure_single_stepping(C= PUState *cpu, return S_OK; } =20 -/* Tries to find a breakpoint at the specified address. */ -static struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t add= ress) -{ - struct whpx_state *whpx =3D &whpx_global; - int i; - - if (whpx->breakpoints.breakpoints) { - for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { - if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { - return &whpx->breakpoints.breakpoints->data[i]; - } - } - } - - return NULL; -} - /* * Linux uses int3 (0xCC) during startup (see int3_selftest()) and for * debugging user-mode applications. Since the WHPX API does not offer @@ -1136,7 +1102,7 @@ static const uint8_t whpx_breakpoint_instruction =3D = 0xF1; * memory, but doesn't actually do it. The memory accessing is done in * whpx_apply_breakpoints(). */ -static void whpx_translate_cpu_breakpoints( +void whpx_translate_cpu_breakpoints( struct whpx_breakpoints *breakpoints, CPUState *cpu, int cpu_breakpoint_count) @@ -1230,7 +1196,7 @@ static void whpx_translate_cpu_breakpoints( * Passing resuming=3Dtrue will try to set all previously unset breakpoin= ts. * Passing resuming=3Dfalse will remove all inserted ones. */ -static void whpx_apply_breakpoints( +void whpx_apply_breakpoints( struct whpx_breakpoint_collection *breakpoints, CPUState *cpu, bool resuming) @@ -1306,93 +1272,6 @@ static void whpx_apply_breakpoints( } } =20 -/* - * This function is called when the a VCPU is about to start and no other - * VCPUs have been started so far. Since the VCPU start order could be - * arbitrary, it doesn't have to be VCPU#0. - * - * It is used to commit the breakpoints into memory, and configure WHPX - * to intercept debug exceptions. - * - * Note that whpx_set_exception_exit_bitmap() cannot be called if one or - * more VCPUs are already running, so this is the best place to do it. - */ -static int whpx_first_vcpu_starting(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - g_assert(bql_locked()); - - if (!QTAILQ_EMPTY(&cpu->breakpoints) || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - CPUBreakpoint *bp; - int i =3D 0; - bool update_pending =3D false; - - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (i >=3D whpx->breakpoints.original_address_count || - bp->pc !=3D whpx->breakpoints.original_addresses[i]) { - update_pending =3D true; - } - - i++; - } - - if (i !=3D whpx->breakpoints.original_address_count) { - update_pending =3D true; - } - - if (update_pending) { - /* - * The CPU breakpoints have changed since the last call to - * whpx_translate_cpu_breakpoints(). WHPX breakpoints must - * now be recomputed. - */ - whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); - } - - /* Actually insert the breakpoints into the memory. */ - whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); - } - - uint64_t exception_mask; - if (whpx->step_pending || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - /* - * We are either attempting to single-step one or more CPUs, or - * have one or more breakpoints enabled. Both require intercepting - * the WHvX64ExceptionTypeBreakpointTrap exception. - */ - - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; - } else { - /* Let the guest handle all exceptions. */ - exception_mask =3D 0; - } - - hr =3D whpx_set_exception_exit_bitmap(exception_mask); - if (!SUCCEEDED(hr)) { - error_report("WHPX: Failed to update exception exit mask," - "hr=3D%08lx.", hr); - return 1; - } - - return 0; -} - -/* - * This function is called when the last VCPU has finished running. - * It is used to remove any previously set breakpoints from memory. - */ -static int whpx_last_vcpu_stopping(CPUState *cpu) -{ - whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); - return 0; -} - /* Returns the address of the next instruction that is about to be execute= d. */ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) { @@ -1633,7 +1512,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) } } =20 -static int whpx_vcpu_run(CPUState *cpu) +int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; @@ -2056,65 +1935,6 @@ static int whpx_vcpu_run(CPUState *cpu) return ret < 0; } =20 -static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) -{ - if (!cpu->vcpu_dirty) { - whpx_get_registers(cpu); - cpu->vcpu_dirty =3D true; - } -} - -static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_RESET_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_FULL_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty =3D true; -} - -/* - * CPU support. - */ - -void whpx_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -void whpx_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - -static void whpx_pre_resume_vm(AccelState *as, bool step_pending) -{ - whpx_global.step_pending =3D step_pending; -} - /* * Vcpu support. */ @@ -2243,295 +2063,18 @@ error: return ret; } =20 -int whpx_vcpu_exec(CPUState *cpu) -{ - int ret; - int fatal; - - for (;;) { - if (cpu->exception_index >=3D EXCP_INTERRUPT) { - ret =3D cpu->exception_index; - cpu->exception_index =3D -1; - break; - } - - fatal =3D whpx_vcpu_run(cpu); - - if (fatal) { - error_report("WHPX: Failed to exec a virtual processor"); - abort(); - } - } - - return ret; -} - -void whpx_destroy_vcpu(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D cpu->accel; - - whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); - whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); - g_free(cpu->accel); -} - -void whpx_vcpu_kick(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - whp_dispatch.WHvCancelRunVirtualProcessor( - whpx->partition, cpu->cpu_index, 0); -} - -/* - * Memory support. - */ - -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); - } - */ - - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { - hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); - } - - if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); - } -} - -static void whpx_process_section(MemoryRegionSection *section, int add) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - - if (!memory_region_is_ram(mr)) { - return; - } - - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); -} - -static void whpx_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - memory_region_ref(section->mr); - whpx_process_section(section, 1); -} - -static void whpx_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - whpx_process_section(section, 0); - memory_region_unref(section->mr); -} - -static void whpx_transaction_begin(MemoryListener *listener) -{ -} - -static void whpx_transaction_commit(MemoryListener *listener) -{ -} - -static void whpx_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - MemoryRegion *mr =3D section->mr; - - if (!memory_region_is_ram(mr)) { - return; - } - - memory_region_set_dirty(mr, 0, int128_get64(section->size)); -} - -static MemoryListener whpx_memory_listener =3D { - .name =3D "whpx", - .begin =3D whpx_transaction_begin, - .commit =3D whpx_transaction_commit, - .region_add =3D whpx_region_add, - .region_del =3D whpx_region_del, - .log_sync =3D whpx_log_sync, - .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, -}; - -static void whpx_memory_init(void) -{ - memory_listener_register(&whpx_memory_listener, &address_space_memory); -} - -/* - * Load the functions from the given library, using the given handle. If a - * handle is provided, it is used, otherwise the library is opened. The - * handle will be updated on return with the opened one. - */ -static bool load_whp_dispatch_fns(HMODULE *handle, - WHPFunctionList function_list) -{ - HMODULE hLib =3D *handle; - - #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" - #define WINHV_EMULATION_DLL "WinHvEmulation.dll" - #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - - #define WHP_LOAD_FIELD(return_type, function_name, signature) \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - if (!whp_dispatch.function_name) { \ - error_report("Could not load function %s", #function_name); \ - goto error; \ - } \ - - #define WHP_LOAD_LIB(lib_name, handle_lib) \ - if (!handle_lib) { \ - handle_lib =3D LoadLibrary(lib_name); \ - if (!handle_lib) { \ - error_report("Could not load library %s.", lib_name); \ - goto error; \ - } \ - } \ - - switch (function_list) { - case WINHV_PLATFORM_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_EMULATION_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) - LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_PLATFORM_FNS_SUPPLEMENTAL: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) - break; - } - - *handle =3D hLib; - return true; - -error: - if (hLib) { - FreeLibrary(hLib); - } - - return false; -} - -static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) -{ - struct whpx_state *whpx =3D &whpx_global; - OnOffSplit mode; - - if (!visit_type_OnOffSplit(v, name, &mode, errp)) { - return; - } - - switch (mode) { - case ON_OFF_SPLIT_ON: - whpx->kernel_irqchip_allowed =3D true; - whpx->kernel_irqchip_required =3D true; - break; - - case ON_OFF_SPLIT_OFF: - whpx->kernel_irqchip_allowed =3D false; - whpx->kernel_irqchip_required =3D false; - break; - - case ON_OFF_SPLIT_SPLIT: - error_setg(errp, "WHPX: split irqchip currently not supported"); - error_append_hint(errp, - "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); - break; - - default: - /* - * The value was checked in visit_type_OnOffSplit() above. If - * we get here, then something is wrong in QEMU. - */ - abort(); - } -} - -static void whpx_cpu_instance_init(CPUState *cs) +void whpx_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); } =20 -static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); - - acc->cpu_instance_init =3D whpx_cpu_instance_init; -} - -static const TypeInfo whpx_cpu_accel_type =3D { - .name =3D ACCEL_CPU_NAME("whpx"), - - .parent =3D TYPE_ACCEL_CPU, - .class_init =3D whpx_cpu_accel_class_init, - .abstract =3D true, -}; - /* * Partition support */ =20 -static int whpx_accel_init(AccelState *as, MachineState *ms) +int whpx_accel_init(AccelState *as, MachineState *ms) { struct whpx_state *whpx; int ret; @@ -2714,77 +2257,3 @@ error: =20 return ret; } - -bool whpx_apic_in_platform(void) { - return whpx_global.apic_in_platform; -} - -static void whpx_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelClass *ac =3D ACCEL_CLASS(oc); - ac->name =3D "WHPX"; - ac->init_machine =3D whpx_accel_init; - ac->pre_resume_vm =3D whpx_pre_resume_vm; - ac->allowed =3D &whpx_allowed; - - object_class_property_add(oc, "kernel-irqchip", "on|off|split", - NULL, whpx_set_kernel_irqchip, - NULL, NULL); - object_class_property_set_description(oc, "kernel-irqchip", - "Configure WHPX in-kernel irqchip"); -} - -static void whpx_accel_instance_init(Object *obj) -{ - struct whpx_state *whpx =3D &whpx_global; - - memset(whpx, 0, sizeof(struct whpx_state)); - /* Turn on kernel-irqchip, by default */ - whpx->kernel_irqchip_allowed =3D true; -} - -static const TypeInfo whpx_accel_type =3D { - .name =3D ACCEL_CLASS_NAME("whpx"), - .parent =3D TYPE_ACCEL, - .instance_init =3D whpx_accel_instance_init, - .class_init =3D whpx_accel_class_init, -}; - -static void whpx_type_init(void) -{ - type_register_static(&whpx_accel_type); - type_register_static(&whpx_cpu_accel_type); -} - -bool init_whp_dispatch(void) -{ - if (whp_dispatch_initialized) { - return true; - } - - if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { - goto error; - } - - if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { - goto error; - } - - assert(load_whp_dispatch_fns(&hWinHvPlatform, - WINHV_PLATFORM_FNS_SUPPLEMENTAL)); - whp_dispatch_initialized =3D true; - - return true; -error: - if (hWinHvPlatform) { - FreeLibrary(hWinHvPlatform); - } - - if (hWinHvEmulation) { - FreeLibrary(hWinHvEmulation); - } - - return false; -} - -type_init(whpx_type_init); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695421; cv=none; d=zohomail.com; s=zohoarc; b=emIEGsMN+LvtTeQ2Cha8vqet/K02qX3pNqPX8JpQ69EbEnmTrXcS235H/Tb+r9AfNAJU4ilYRcO1SHTARd6Rrj2rufTJ8YACyxcJHSDTXwI2JdU2all1TU59AW0DHpEqYAJ7QTPpYYQapRLQSCxUpXIQ8N/yUx72pXKcdYokt8Q= ARC-Message-Signature: i=1; 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s=sig1; bh=1HDLl+vsTco3N+tEGqvISSZb2bm2NYHKpsf2pCMBzc0=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=YhmXj4iWI4HJh/0x3IVSgDszfALMhfq11gliN4XXk/mSABe/DNLp4PK7tYEhzd/1K2SzmPi/kZ9/67x/uHznUib3xHO5i6hKQK0R9oYTMARq6rMMG9TH2Pkd2Luf9A9gQRzJaua+hF14IZzl4HTxFOmQay0UJFCkPExQbGkqMhkN5SS/vfyFo5VPfJ9cGCxVugZwLtHaYIGfJ/SuNnisf6vpt6zBZBi5XrjRZ2lszFufBZeBXGKG8q+Z/ThzSpLNRS/H0iALYZX8KGvdBgoFq6McT3TRRbgz/gRb9ERPkbemelkD9v4t9lL9gMGstDMUOz7h3zYL6VeF5a20VIkRbA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: mohamed@unpredictable.fr, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Phil Dennis-Jordan , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Richard Henderson , Pedro Barbuda , Pierrick Bouvier Subject: [PATCH v9 08/27] whpx: ifdef out winhvemulation on non-x86_64 Date: Wed, 29 Oct 2025 00:47:38 +0100 Message-ID: <20251028234757.39609-9-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251028234757.39609-1-mohamed@unpredictable.fr> References: <20251028234757.39609-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: hvE44vxaJSZq5ABCVQWMHx7t55LpEPEn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDIwMiBTYWx0ZWRfX0J1LgiUp0nt8 Kj9Ag5Y7DQJqqVGcYxbtXCdpjxvT9giVXaKtmN0EHBIbMu9FLHbWKrHNuQ+4wEEnPuij2o0gMhl yHI7tAgANyi+lFjYxhv70F4OX4fwr+Edu90nmXpx/tUIv2aPPGaEk+80R8bSaBIzYpPG3/g4RcV ju4oI6rDQYMk2qazx5COzv1SrcxiA3hyvxtsjK/6husJODPe0GHX56fb6jXpRxEQkLQGCQabu6B HNERsWMeFZQ3fvIYOdSTzm8kM+PeFE/C/cXg9uyLQ+rCEBnocxYDEpSIUQtomkdGuctmadetc= X-Proofpoint-ORIG-GUID: hvE44vxaJSZq5ABCVQWMHx7t55LpEPEn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_09,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=767 spamscore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 clxscore=1030 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510280202 X-JNJ: AAAAAAABebvpXY+dYVo6E7x8swO0UuX70KoLXs06gDSsxpqLVvbkpJAkZ1FwsQN9GU7x/EYR43whoDvyv1/1UtDnhL4z8fr4nOectjt9oKl6FSrmGkWOq8C0hWucuNoLRsZcwoWphQAELPn25J6PJexrVl3az6DVA/6M7y8+QqABJPbZ+ft9F+cHzqZGw7hZWgndyM1K0mQ+WJOX3onGGqWW3J2TguTfqDwbM5ueTcvg/Z8lXE3eXLzcXvlb/mHGOu6ueJg86+96WRW3riXvqR0mT5cBU/9Wj/ykpXCrdMHAhVXEn7m20dM2hL/uVvriGC8quk10soQuggJo5NnxCMK8ex9kxQ7lg27BczCEoM3vKPpxHeDJ0tZ7IyxXpnwPbfIS7+uxIiMUbKrL6aWaThnE9HHf+K53TJ+F2aMkMlGQdJzmXkgMjECHdOvucM0evVOldi0MbxerrzUVrKil45v9v41hfkLEWJ8y7yKPIGa3kiHsGna1jo+GFhonrqWYgKXs2BygdsFcahdQdqwKvq3c2bCYTDPcGAPrWsHgxCPP8omRFtDaiMJy3mJ9x28srlzf2OIeYm8A8tjkOZLS86sEbsZTfQ2SeGk5+t1mhMO6/4BrWi1qqpx0aaikRLGFFpmE3fnc2Wxr0DXsfe6cxytG2d0akQm1to4q/Ro+chaNCww5YD/N/lJ3PJ9hdNstDHejA4WRWGNhu8tR4reba2vZGZxC/+I5mSgWcU8lYF9BSsUcqW17RHd7 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" winhvemulation is x86_64 only. In the future, we might want to get rid of winhvemulation usage entirely. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 14 ++++++++++++-- include/system/whpx-common.h | 2 ++ include/system/whpx-internal.h | 7 ++++++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 66c9238586..95664a1df7 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -41,7 +41,9 @@ bool whpx_allowed; static bool whp_dispatch_initialized; static HMODULE hWinHvPlatform; +#ifdef __x86_64__ static HMODULE hWinHvEmulation; +#endif =20 struct whpx_state whpx_global; struct WHPDispatch whp_dispatch; @@ -236,8 +238,10 @@ void whpx_destroy_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); +#ifdef __x86_64__ AccelCPUState *vcpu =3D cpu->accel; whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); +#endif g_free(cpu->accel); } =20 @@ -412,8 +416,12 @@ static bool load_whp_dispatch_fns(HMODULE *handle, LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) break; case WINHV_EMULATION_FNS_DEFAULT: +#ifdef __x86_64__ WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) +#else + g_assert_not_reached(); +#endif break; case WINHV_PLATFORM_FNS_SUPPLEMENTAL: WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) @@ -539,11 +547,11 @@ bool init_whp_dispatch(void) if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { goto error; } - +#ifdef __x86_64__ if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { goto error; } - +#endif assert(load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_SUPPLEMENTAL)); whp_dispatch_initialized =3D true; @@ -553,9 +561,11 @@ error: if (hWinHvPlatform) { FreeLibrary(hWinHvPlatform); } +#ifdef __x86_64__ if (hWinHvEmulation) { FreeLibrary(hWinHvEmulation); } +#endif return false; } =20 diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index e549c7539c..7a7c607e0a 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -3,7 +3,9 @@ #define SYSTEM_WHPX_COMMON_H =20 struct AccelCPUState { +#ifdef __x86_64__ WHV_EMULATOR_HANDLE emulator; +#endif bool window_registered; bool interruptable; bool ready_for_pic_interrupt; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index c59f9de091..4565436682 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -4,8 +4,9 @@ =20 #include #include +#ifdef __x86_64__ #include - +#endif #include "hw/i386/apic.h" =20 typedef enum WhpxBreakpointState { @@ -100,12 +101,16 @@ void whpx_apic_get(APICCommonState *s); =20 /* Define function typedef */ LIST_WINHVPLATFORM_FUNCTIONS(WHP_DEFINE_TYPE) +#ifdef __x86_64__ LIST_WINHVEMULATION_FUNCTIONS(WHP_DEFINE_TYPE) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DEFINE_TYPE) =20 struct WHPDispatch { LIST_WINHVPLATFORM_FUNCTIONS(WHP_DECLARE_MEMBER) +#ifdef __x86_64__ LIST_WINHVEMULATION_FUNCTIONS(WHP_DECLARE_MEMBER) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DECLARE_MEMBER) }; =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" As of why: WHPX on arm64 doesn't have debug trap support as of today. Keep the exception bitmap interface for now - despite that being entirely u= navailable on arm64 too. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 2 +- include/system/whpx-common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 95664a1df7..c0ff6cacb8 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -123,7 +123,7 @@ int whpx_first_vcpu_starting(CPUState *cpu) * have one or more breakpoints enabled. Both require intercepting * the WHvX64ExceptionTypeBreakpointTrap exception. */ - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + exception_mask =3D 1UL << WHPX_INTERCEPT_DEBUG_TRAPS; } else { /* Let the guest handle all exceptions. */ exception_mask =3D 0; diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index 7a7c607e0a..73b9f7c119 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -20,4 +20,7 @@ int whpx_first_vcpu_starting(CPUState *cpu); int whpx_last_vcpu_stopping(CPUState *cpu); void whpx_memory_init(void); struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); + +/* On x64: same as WHvX64ExceptionTypeDebugTrapOrFault */ +#define WHPX_INTERCEPT_DEBUG_TRAPS 1 #endif --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.242; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761696013575158500 Content-Type: text/plain; charset="utf-8" Change terminology to match the KVM one, as APIC is x86-specific. Signed-off-by: Mohamed Mediouni Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-accel-ops.c | 2 +- accel/whpx/whpx-common.c | 4 ++-- hw/i386/x86-cpu.c | 4 ++-- include/system/whpx-internal.h | 2 +- include/system/whpx.h | 4 ++-- target/i386/cpu-apic.c | 2 +- target/i386/whpx/whpx-all.c | 14 +++++++------- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/accel/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c index c84a25c273..50fadea0fd 100644 --- a/accel/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -78,7 +78,7 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) =20 static bool whpx_vcpu_thread_is_idle(CPUState *cpu) { - return !whpx_apic_in_platform(); + return !whpx_irqchip_in_kernel(); } =20 static void whpx_accel_ops_class_init(ObjectClass *oc, const void *data) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c0ff6cacb8..18d93225c1 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -496,9 +496,9 @@ static const TypeInfo whpx_cpu_accel_type =3D { * Partition support */ =20 -bool whpx_apic_in_platform(void) +bool whpx_irqchip_in_kernel(void) { - return whpx_global.apic_in_platform; + return whpx_global.kernel_irqchip; } =20 static void whpx_accel_class_init(ObjectClass *oc, const void *data) diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c index 1a86a853d5..aee7fc76f5 100644 --- a/hw/i386/x86-cpu.c +++ b/hw/i386/x86-cpu.c @@ -45,7 +45,7 @@ static void pic_irq_request(void *opaque, int irq, int le= vel) =20 trace_x86_pic_interrupt(irq, level); if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && - !whpx_apic_in_platform()) { + !whpx_irqchip_in_kernel()) { CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); if (apic_accept_pic_intr(cpu->apic_state)) { @@ -71,7 +71,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) X86CPU *cpu =3D env_archcpu(env); int intno; =20 - if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { + if (!kvm_irqchip_in_kernel() && !whpx_irqchip_in_kernel()) { intno =3D apic_get_interrupt(cpu->apic_state); if (intno >=3D 0) { return intno; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 4565436682..81c0c1819f 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -44,7 +44,7 @@ struct whpx_state { =20 bool kernel_irqchip_allowed; bool kernel_irqchip_required; - bool apic_in_platform; + bool kernel_irqchip; }; =20 extern struct whpx_state whpx_global; diff --git a/include/system/whpx.h b/include/system/whpx.h index 00f6a3e523..98fe045ba1 100644 --- a/include/system/whpx.h +++ b/include/system/whpx.h @@ -26,10 +26,10 @@ #ifdef CONFIG_WHPX_IS_POSSIBLE extern bool whpx_allowed; #define whpx_enabled() (whpx_allowed) -bool whpx_apic_in_platform(void); +bool whpx_irqchip_in_kernel(void); #else /* !CONFIG_WHPX_IS_POSSIBLE */ #define whpx_enabled() 0 -#define whpx_apic_in_platform() (0) +#define whpx_irqchip_in_kernel() (0) #endif /* !CONFIG_WHPX_IS_POSSIBLE */ =20 #endif /* QEMU_WHPX_H */ diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index 564c1288e4..c0492035b8 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -32,7 +32,7 @@ APICCommonClass *apic_get_class(Error **errp) apic_type =3D "kvm-apic"; } else if (xen_enabled()) { apic_type =3D "xen-apic"; - } else if (whpx_apic_in_platform()) { + } else if (whpx_irqchip_in_kernel()) { apic_type =3D "whpx-apic"; } =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d1f8e49cb2..feabbec427 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -607,7 +607,7 @@ void whpx_get_registers(CPUState *cpu) hr); } =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -749,7 +749,7 @@ void whpx_get_registers(CPUState *cpu) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { whpx_apic_get(x86_cpu->apic_state); } =20 @@ -1379,7 +1379,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Get pending hard interruption or replay one that was overwritten */ - if (!whpx_apic_in_platform()) { + if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); @@ -1552,7 +1552,7 @@ int whpx_vcpu_run(CPUState *cpu) =20 if (exclusive_step_mode =3D=3D WHPX_STEP_NONE) { whpx_vcpu_process_async_events(cpu); - if (cpu->halted && !whpx_apic_in_platform()) { + if (cpu->halted && !whpx_irqchip_in_kernel()) { cpu->exception_index =3D EXCP_HLT; qatomic_set(&cpu->exit_request, false); return 0; @@ -1641,7 +1641,7 @@ int whpx_vcpu_run(CPUState *cpu) break; =20 case WHvRunVpExitReasonX64ApicEoi: - assert(whpx_apic_in_platform()); + assert(whpx_irqchip_in_kernel()); ioapic_eoi_broadcast(vcpu->exit_ctx.ApicEoi.InterruptVector); break; =20 @@ -2186,7 +2186,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } } else { - whpx->apic_in_platform =3D true; + whpx->kernel_irqchip =3D true; } } =20 @@ -2195,7 +2195,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) prop.ExtendedVmExits.X64MsrExit =3D 1; prop.ExtendedVmExits.X64CpuidExit =3D 1; prop.ExtendedVmExits.ExceptionExit =3D 1; - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { prop.ExtendedVmExits.X64ApicInitSipiExitTrap =3D 1; } =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.203; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695569599154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 3 + hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_whpx.c | 239 +++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/arm_gicv3_common.h | 3 + 5 files changed, 249 insertions(+) create mode 100644 hw/intc/arm_gicv3_whpx.c diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 61d7bab803..9121eb37eb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -47,6 +47,7 @@ #include "system/tcg.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" #include "system/qtest.h" #include "system/system.h" #include "hw/loader.h" @@ -2105,6 +2106,8 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; + } else if (whpx_enabled()) { + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 2d0df6da86..1fd1e329e8 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/whpx.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -663,6 +664,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (whpx_enabled()) { + return TYPE_WHPX_GICV3; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c new file mode 100644 index 0000000000..88a05e5901 --- /dev/null +++ b/hw/intc/arm_gicv3_whpx.c @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/whpx.h" +#include "system/whpx-internal.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" + +#include "hw/arm/bsa.h" +#include +#include +#include + +struct WHPXARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +typedef struct WHPXARMGICv3Class WHPXARMGICv3Class; + +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3State, WHPXARMGICv3Class, + WHPX_GICV3, TYPE_WHPX_GICV3); + +/* TODO: Implement GIC state save-restore */ +static void whpx_gicv3_check(GICv3State *s) +{ +} + +static void whpx_gicv3_put(GICv3State *s) +{ + whpx_gicv3_check(s); +} + +static void whpx_gicv3_get(GICv3State *s) +{ +} + +static void whpx_gicv3_set_irq(void *opaque, int irq, int level) +{ + struct whpx_state *whpx =3D &whpx_global; + + GICv3State *s =3D (GICv3State *)opaque; + if (irq > s->num_irq) { + return; + } + WHV_INTERRUPT_TYPE interrupt_type =3D WHvArm64InterruptTypeFixed; + WHV_INTERRUPT_CONTROL interrupt_control =3D { + interrupt_type =3D WHvArm64InterruptTypeFixed, + .RequestedVector =3D GIC_INTERNAL + irq, .InterruptControl.Asserted = =3D level}; + + whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control, + sizeof(interrupt_control)); +} + +static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3State *s; + GICv3CPUState *c; + + c =3D (GICv3CPUState *)env->gicv3state; + s =3D c->gic; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); + + if (s->migration_blocker) { + return; + } + + c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; +} + +static void whpx_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + whpx_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D whpx_gicv3_icc_reset, + }, +}; + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_gicv3_realize(DeviceState *dev, Error **errp) +{ + GICv3State *s =3D WHPX_GICV3(dev); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + Error *local_err =3D NULL; + int i; + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by WHPX"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + CPUState *cpu_state =3D qemu_get_cpu(i); + ARMCPU *cpu =3D ARM_CPU(cpu_state); + WHV_REGISTER_VALUE val =3D {.Reg64 =3D 0x080A0000 + (GICV3_REDIST_= SIZE * i)}; + whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val); + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq) { + error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); + return; + } +} + +static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_CLASS(klass); + + agcc->pre_save =3D whpx_gicv3_get; + agcc->post_load =3D whpx_gicv3_put; + + device_class_set_parent_realize(dc, whpx_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NU= LL, + &kgc->parent_phases); +} + +static const TypeInfo whpx_arm_gicv3_info =3D { + .name =3D TYPE_WHPX_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D whpx_gicv3_class_init, + .class_size =3D sizeof(WHPXARMGICv3Class), +}; + +static void whpx_gicv3_register_types(void) +{ + type_register_static(&whpx_arm_gicv3_info); +} + +type_init(whpx_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index faae20b93d..96742df090 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic= .c', 'apic_common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) +specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('a= rm_gicv3_whpx.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 61d51915e0..9fd8b9b858 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -313,6 +313,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.228; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695878614154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 1 + target/arm/meson.build | 1 + target/arm/whpx/meson.build | 3 + target/arm/whpx/whpx-all.c | 845 ++++++++++++++++++++++++++++++++++++ 4 files changed, 850 insertions(+) create mode 100644 target/arm/whpx/meson.build create mode 100644 target/arm/whpx/whpx-all.c diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 18d93225c1..c69792e638 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -16,6 +16,7 @@ #include "gdbstub/helpers.h" #include "qemu/accel.h" #include "accel/accel-ops.h" +#include "system/memory.h" #include "system/whpx.h" #include "system/cpus.h" #include "system/runstate.h" diff --git a/target/arm/meson.build b/target/arm/meson.build index 3df7e03654..61277a627c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -59,6 +59,7 @@ arm_common_system_ss.add(files( )) =20 subdir('hvf') +subdir('whpx') =20 if 'CONFIG_TCG' in config_all_accel subdir('tcg') diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build new file mode 100644 index 0000000000..1de2ef0283 --- /dev/null +++ b/target/arm/whpx/meson.build @@ -0,0 +1,3 @@ +arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', +)) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c new file mode 100644 index 0000000000..8c34650765 --- /dev/null +++ b/target/arm/whpx/whpx-all.c @@ -0,0 +1,845 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "syndrome.h" +#include "cpu.h" +#include "target/arm/cpregs.h" +#include "internals.h" + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" +#include "hw/arm/bsa.h" +#include "arm-powerctl.h" + +#include +#include + +struct whpx_reg_match { + WHV_REGISTER_NAME reg; + uint64_t offset; +}; + +static const struct whpx_reg_match whpx_reg_match[] =3D { + { WHvArm64RegisterX0, offsetof(CPUARMState, xregs[0]) }, + { WHvArm64RegisterX1, offsetof(CPUARMState, xregs[1]) }, + { WHvArm64RegisterX2, offsetof(CPUARMState, xregs[2]) }, + { WHvArm64RegisterX3, offsetof(CPUARMState, xregs[3]) }, + { WHvArm64RegisterX4, offsetof(CPUARMState, xregs[4]) }, + { WHvArm64RegisterX5, offsetof(CPUARMState, xregs[5]) }, + { WHvArm64RegisterX6, offsetof(CPUARMState, xregs[6]) }, + { WHvArm64RegisterX7, offsetof(CPUARMState, xregs[7]) }, + { WHvArm64RegisterX8, offsetof(CPUARMState, xregs[8]) }, + { WHvArm64RegisterX9, offsetof(CPUARMState, xregs[9]) }, + { WHvArm64RegisterX10, offsetof(CPUARMState, xregs[10]) }, + { WHvArm64RegisterX11, offsetof(CPUARMState, xregs[11]) }, + { WHvArm64RegisterX12, offsetof(CPUARMState, xregs[12]) }, + { WHvArm64RegisterX13, offsetof(CPUARMState, xregs[13]) }, + { WHvArm64RegisterX14, offsetof(CPUARMState, xregs[14]) }, + { WHvArm64RegisterX15, offsetof(CPUARMState, xregs[15]) }, + { WHvArm64RegisterX16, offsetof(CPUARMState, xregs[16]) }, + { WHvArm64RegisterX17, offsetof(CPUARMState, xregs[17]) }, + { WHvArm64RegisterX18, offsetof(CPUARMState, xregs[18]) }, + { WHvArm64RegisterX19, offsetof(CPUARMState, xregs[19]) }, + { WHvArm64RegisterX20, offsetof(CPUARMState, xregs[20]) }, + { WHvArm64RegisterX21, offsetof(CPUARMState, xregs[21]) }, + { WHvArm64RegisterX22, offsetof(CPUARMState, xregs[22]) }, + { WHvArm64RegisterX23, offsetof(CPUARMState, xregs[23]) }, + { WHvArm64RegisterX24, offsetof(CPUARMState, xregs[24]) }, + { WHvArm64RegisterX25, offsetof(CPUARMState, xregs[25]) }, + { WHvArm64RegisterX26, offsetof(CPUARMState, xregs[26]) }, + { WHvArm64RegisterX27, offsetof(CPUARMState, xregs[27]) }, + { WHvArm64RegisterX28, offsetof(CPUARMState, xregs[28]) }, + { WHvArm64RegisterFp, offsetof(CPUARMState, xregs[29]) }, + { WHvArm64RegisterLr, offsetof(CPUARMState, xregs[30]) }, + { WHvArm64RegisterPc, offsetof(CPUARMState, pc) }, +}; + +static const struct whpx_reg_match whpx_fpreg_match[] =3D { + { WHvArm64RegisterQ0, offsetof(CPUARMState, vfp.zregs[0]) }, + { WHvArm64RegisterQ1, offsetof(CPUARMState, vfp.zregs[1]) }, + { WHvArm64RegisterQ2, offsetof(CPUARMState, vfp.zregs[2]) }, + { WHvArm64RegisterQ3, offsetof(CPUARMState, vfp.zregs[3]) }, + { WHvArm64RegisterQ4, offsetof(CPUARMState, vfp.zregs[4]) }, + { WHvArm64RegisterQ5, offsetof(CPUARMState, vfp.zregs[5]) }, + { WHvArm64RegisterQ6, offsetof(CPUARMState, vfp.zregs[6]) }, + { WHvArm64RegisterQ7, offsetof(CPUARMState, vfp.zregs[7]) }, + { WHvArm64RegisterQ8, offsetof(CPUARMState, vfp.zregs[8]) }, + { WHvArm64RegisterQ9, offsetof(CPUARMState, vfp.zregs[9]) }, + { WHvArm64RegisterQ10, offsetof(CPUARMState, vfp.zregs[10]) }, + { WHvArm64RegisterQ11, offsetof(CPUARMState, vfp.zregs[11]) }, + { WHvArm64RegisterQ12, offsetof(CPUARMState, vfp.zregs[12]) }, + { WHvArm64RegisterQ13, offsetof(CPUARMState, vfp.zregs[13]) }, + { WHvArm64RegisterQ14, offsetof(CPUARMState, vfp.zregs[14]) }, + { WHvArm64RegisterQ15, offsetof(CPUARMState, vfp.zregs[15]) }, + { WHvArm64RegisterQ16, offsetof(CPUARMState, vfp.zregs[16]) }, + { WHvArm64RegisterQ17, offsetof(CPUARMState, vfp.zregs[17]) }, + { WHvArm64RegisterQ18, offsetof(CPUARMState, vfp.zregs[18]) }, + { WHvArm64RegisterQ19, offsetof(CPUARMState, vfp.zregs[19]) }, + { WHvArm64RegisterQ20, offsetof(CPUARMState, vfp.zregs[20]) }, + { WHvArm64RegisterQ21, offsetof(CPUARMState, vfp.zregs[21]) }, + { WHvArm64RegisterQ22, offsetof(CPUARMState, vfp.zregs[22]) }, + { WHvArm64RegisterQ23, offsetof(CPUARMState, vfp.zregs[23]) }, + { WHvArm64RegisterQ24, offsetof(CPUARMState, vfp.zregs[24]) }, + { WHvArm64RegisterQ25, offsetof(CPUARMState, vfp.zregs[25]) }, + { WHvArm64RegisterQ26, offsetof(CPUARMState, vfp.zregs[26]) }, + { WHvArm64RegisterQ27, offsetof(CPUARMState, vfp.zregs[27]) }, + { WHvArm64RegisterQ28, offsetof(CPUARMState, vfp.zregs[28]) }, + { WHvArm64RegisterQ29, offsetof(CPUARMState, vfp.zregs[29]) }, + { WHvArm64RegisterQ30, offsetof(CPUARMState, vfp.zregs[30]) }, + { WHvArm64RegisterQ31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +struct whpx_sreg_match { + WHV_REGISTER_NAME reg; + uint32_t key; + bool global; + uint32_t cp_idx; +}; + +static struct whpx_sreg_match whpx_sreg_match[] =3D { + { WHvArm64RegisterDbgbvr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 7) }, +#ifdef SYNC_NO_RAW_REGS + /* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easi= er. + */ + { WHvArm64RegisterMidrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 0, 0) }, + { WHvArm64RegisterMpidrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 0, 5) }, + { WHvArm64RegisterIdPfr0El1, ENCODE_AA64_CP_REG(0, 4, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Pfr1El1, ENCODE_AA64_CP_REG(0, 4, 3, 0, 1), tr= ue }, + { WHvArm64RegisterIdAa64Dfr0El1, ENCODE_AA64_CP_REG(0, 5, 3, 0, 0), tr= ue }, + { WHvArm64RegisterIdAa64Dfr1El1, ENCODE_AA64_CP_REG(0, 5, 3, 0, 1), tr= ue }, + { WHvArm64RegisterIdAa64Isar0El1, ENCODE_AA64_CP_REG(0, 6, 3, 0, 0), t= rue }, + { WHvArm64RegisterIdAa64Isar1El1, ENCODE_AA64_CP_REG(0, 6, 3, 0, 1), t= rue }, +#ifdef SYNC_NO_MMFR0 + /* We keep the hardware MMFR0 around. HW limits are there anyway */ + { WHvArm64RegisterIdAa64Mmfr0El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Mmfr1El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 1), t= rue }, + { WHvArm64RegisterIdAa64Mmfr2El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 2), t= rue }, + { WHvArm64RegisterIdAa64Mmfr3El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 3), t= rue }, + + { WHvArm64RegisterMdscrEl1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 2) }, + { WHvArm64RegisterSctlrEl1, ENCODE_AA64_CP_REG(1, 0, 3, 0, 0) }, + { WHvArm64RegisterCpacrEl1, ENCODE_AA64_CP_REG(1, 0, 3, 0, 2) }, + { WHvArm64RegisterTtbr0El1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 0) }, + { WHvArm64RegisterTtbr1El1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 1) }, + { WHvArm64RegisterTcrEl1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 2) }, + + { WHvArm64RegisterApiAKeyLoEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 0) }, + { WHvArm64RegisterApiAKeyHiEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 1) }, + { WHvArm64RegisterApiBKeyLoEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 2) }, + { WHvArm64RegisterApiBKeyHiEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 3) }, + { WHvArm64RegisterApdAKeyLoEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 0) }, + { WHvArm64RegisterApdAKeyHiEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 1) }, + { WHvArm64RegisterApdBKeyLoEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 2) }, + { WHvArm64RegisterApdBKeyHiEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 3) }, + { WHvArm64RegisterApgAKeyLoEl1, ENCODE_AA64_CP_REG(2, 3, 3, 0, 0) }, + { WHvArm64RegisterApgAKeyHiEl1, ENCODE_AA64_CP_REG(2, 3, 3, 0, 1) }, + + { WHvArm64RegisterSpsrEl1, ENCODE_AA64_CP_REG(4, 0, 3, 0, 0) }, + { WHvArm64RegisterElrEl1, ENCODE_AA64_CP_REG(4, 0, 3, 0, 1) }, + { WHvArm64RegisterSpEl1, ENCODE_AA64_CP_REG(4, 1, 3, 0, 0) }, + { WHvArm64RegisterEsrEl1, ENCODE_AA64_CP_REG(5, 2, 3, 0, 0) }, + { WHvArm64RegisterFarEl1, ENCODE_AA64_CP_REG(6, 0, 3, 0, 0) }, + { WHvArm64RegisterParEl1, ENCODE_AA64_CP_REG(7, 4, 3, 0, 0) }, + { WHvArm64RegisterMairEl1, ENCODE_AA64_CP_REG(10, 2, 3, 0, 0) }, + { WHvArm64RegisterVbarEl1, ENCODE_AA64_CP_REG(12, 0, 3, 0, 0) }, + { WHvArm64RegisterContextidrEl1, ENCODE_AA64_CP_REG(13, 0, 3, 0, 1) }, + { WHvArm64RegisterTpidrEl1, ENCODE_AA64_CP_REG(13, 0, 3, 0, 4) }, + { WHvArm64RegisterCntkctlEl1, ENCODE_AA64_CP_REG(14, 1, 3, 0, 0) }, + { WHvArm64RegisterCsselrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 2, 0) }, + { WHvArm64RegisterTpidrEl0, ENCODE_AA64_CP_REG(13, 0, 3, 3, 2) }, + { WHvArm64RegisterTpidrroEl0, ENCODE_AA64_CP_REG(13, 0, 3, 3, 3) }, + { WHvArm64RegisterCntvCtlEl0, ENCODE_AA64_CP_REG(14, 3, 3, 3, 1) }, + { WHvArm64RegisterCntvCvalEl0, ENCODE_AA64_CP_REG(14, 3, 3, 3, 2) }, + { WHvArm64RegisterSpEl1, ENCODE_AA64_CP_REG(4, 1, 3, 4, 0) }, +}; + +static void flush_cpu_state(CPUState *cpu) +{ + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } +} + +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +{ + if (exceptions !=3D 0) { + return E_NOTIMPL; + } + return ERROR_SUCCESS; +} +void whpx_apply_breakpoints( +struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming) +{ + +} +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count) +{ + +} + +static void whpx_get_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE* val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + flush_cpu_state(cpu); + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_get_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = *val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static uint64_t whpx_get_gp_reg(CPUState *cpu, int rt) +{ + assert(rt <=3D 31); + if (rt =3D=3D 31) { + return 0; + } + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE val; + whpx_get_reg(cpu, reg, &val); + + return val.Reg64; +} + +static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val) +{ + assert(rt < 31); + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE reg_val =3D {.Reg64 =3D val}; + + whpx_set_reg(cpu, reg, reg_val); +} + +static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) +{ + uint64_t syndrome =3D ctx->Syndrome; + + bool isv =3D syndrome & ARM_EL_ISV; + bool iswrite =3D (syndrome >> 6) & 1; + bool sse =3D (syndrome >> 21) & 1; + uint32_t sas =3D (syndrome >> 22) & 3; + uint32_t len =3D 1 << sas; + uint32_t srt =3D (syndrome >> 16) & 0x1f; + uint32_t cm =3D (syndrome >> 8) & 0x1; + uint64_t val =3D 0; + + assert(!cm); + assert(isv); + + if (iswrite) { + val =3D whpx_get_gp_reg(cpu, srt); + address_space_write(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + } else { + address_space_read(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + if (sse) { + val =3D sextract64(val, 0, len * 8); + } + whpx_set_gp_reg(cpu, srt, val); + } + + return 0; +} + +static void whpx_psci_cpu_off(ARMCPU *arm_cpu) +{ + int32_t ret =3D arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); + assert(ret =3D=3D QEMU_ARM_POWERCTL_RET_SUCCESS); +} + +int whpx_vcpu_run(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + AccelCPUState *vcpu =3D cpu->accel; + int ret; + + + g_assert(bql_locked()); + + if (whpx->running_cpus++ =3D=3D 0) { + ret =3D whpx_first_vcpu_starting(cpu); + if (ret !=3D 0) { + return ret; + } + } + + bql_unlock(); + + + cpu_exec_start(cpu); + do { + bool advance_pc =3D false; + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } + + if (qatomic_read(&cpu->exit_request)) { + whpx_vcpu_kick(cpu); + } + + hr =3D whp_dispatch.WHvRunVirtualProcessor( + whpx->partition, cpu->cpu_index, + &vcpu->exit_ctx, sizeof(vcpu->exit_ctx)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to exec a virtual processor," + " hr=3D%08lx", hr); + ret =3D -1; + break; + } + + switch (vcpu->exit_ctx.ExitReason) { + case WHvRunVpExitReasonGpaIntercept: + case WHvRunVpExitReasonUnmappedGpa: + advance_pc =3D true; + + if (vcpu->exit_ctx.MemoryAccess.Syndrome >> 8 & 0x1) { + error_report("WHPX: cached access to unmapped memory" + "Pc =3D 0x%llx Gva =3D 0x%llx Gpa =3D 0x%llx", + vcpu->exit_ctx.MemoryAccess.Header.Pc, + vcpu->exit_ctx.MemoryAccess.Gpa, + vcpu->exit_ctx.MemoryAccess.Gva); + break; + } + + ret =3D whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess); + break; + case WHvRunVpExitReasonCanceled: + cpu->exception_index =3D EXCP_INTERRUPT; + ret =3D 1; + break; + case WHvRunVpExitReasonArm64Reset: + switch (vcpu->exit_ctx.Arm64Reset.ResetType) { + case WHvArm64ResetTypePowerOff: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN= ); + break; + case WHvArm64ResetTypeReboot: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + g_assert_not_reached(); + } + bql_lock(); + if (arm_cpu->power_state !=3D PSCI_OFF) { + whpx_psci_cpu_off(arm_cpu); + } + bql_unlock(); + break; + case WHvRunVpExitReasonNone: + case WHvRunVpExitReasonUnrecoverableException: + case WHvRunVpExitReasonInvalidVpRegisterValue: + case WHvRunVpExitReasonUnsupportedFeature: + default: + error_report("WHPX: Unexpected VP exit code 0x%08x", + vcpu->exit_ctx.ExitReason); + whpx_get_registers(cpu); + bql_lock(); + qemu_system_guest_panicked(cpu_get_crash_info(cpu)); + bql_unlock(); + break; + } + if (advance_pc) { + WHV_REGISTER_VALUE pc; + + flush_cpu_state(cpu); + pc.Reg64 =3D vcpu->exit_ctx.MemoryAccess.Header.Pc + 4; + whpx_set_reg(cpu, WHvArm64RegisterPc, pc); + } + } while (!ret); + + cpu_exec_end(cpu); + + bql_lock(); + current_cpu =3D cpu; + + if (--whpx->running_cpus =3D=3D 0) { + whpx_last_vcpu_stopping(cpu); + } + + qatomic_set(&cpu->exit_request, false); + + return ret < 0; +} + +static void clean_whv_register_value(WHV_REGISTER_VALUE *val) +{ + memset(val, 0, sizeof(WHV_REGISTER_VALUE)); +} + +void whpx_get_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + int i; + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + *(uint64_t *)((void *)env + whpx_reg_match[i].offset) =3D val.Reg6= 4; + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + memcpy((void *)env + whpx_fpreg_match[i].offset, &val, sizeof(val.= Reg128)); + } + + whpx_get_reg(cpu, WHvArm64RegisterPc, &val); + env->pc =3D val.Reg64; + + whpx_get_reg(cpu, WHvArm64RegisterFpcr, &val); + vfp_set_fpcr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterFpsr, &val); + vfp_set_fpsr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterPstate, &val); + pstate_write(env, val.Reg32); + + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D true) { + continue; + } + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + whpx_get_reg(cpu, whpx_sreg_match[i].reg, &val); + + arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx] =3D val.Reg64; + } + + /* WHP disallows us from reading global regs as a vCPU */ + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D false) { + continue; + } + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + whpx_get_global_reg(whpx_sreg_match[i].reg, &val); + + arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx] =3D val.Reg64; + } + assert(write_list_to_cpustate(arm_cpu)); + + aarch64_restore_sp(env, arm_current_el(env)); +} + +void whpx_set_registers(CPUState *cpu, int level) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + clean_whv_register_value(&val); + int i; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + val.Reg64 =3D *(uint64_t *)((void *)env + whpx_reg_match[i].offset= ); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + memcpy(&val.Reg128, (void *)env + whpx_fpreg_match[i].offset, size= of(val.Reg128)); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + clean_whv_register_value(&val); + val.Reg64 =3D env->pc; + whpx_set_reg(cpu, WHvArm64RegisterPc, val); + + clean_whv_register_value(&val); + val.Reg32 =3D vfp_get_fpcr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpcr, val); + val.Reg32 =3D vfp_get_fpsr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpsr, val); + val.Reg32 =3D pstate_read(env); + whpx_set_reg(cpu, WHvArm64RegisterPstate, val); + + aarch64_save_sp(env, arm_current_el(env)); + + assert(write_cpustate_to_list(arm_cpu, false)); + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D true) { + continue; + } + + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + clean_whv_register_value(&val); + val.Reg64 =3D arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx]; + whpx_set_reg(cpu, whpx_sreg_match[i].reg, val); + } + + /* Currently set global regs every time. */ + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D false) { + continue; + } + + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + clean_whv_register_value(&val); + val.Reg64 =3D arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx]; + whpx_set_global_reg(whpx_sreg_match[i].reg, val); + } +} + +static uint32_t max_vcpu_index; + +static void whpx_cpu_update_state(void *opaque, bool running, RunState sta= te) +{ +} + +int whpx_init_vcpu(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + AccelCPUState *vcpu =3D NULL; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + int ret; + + uint32_t sregs_match_len =3D ARRAY_SIZE(whpx_sreg_match); + uint32_t sregs_cnt =3D 0; + WHV_REGISTER_VALUE val; + int i; + + vcpu =3D g_new0(AccelCPUState, 1); + + hr =3D whp_dispatch.WHvCreateVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); + if (FAILED(hr)) { + error_report("WHPX: Failed to create a virtual processor," + " hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + /* Assumption that CNTFRQ_EL0 is the same between the VMM and the part= ition. */ + asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); + + cpu->vcpu_dirty =3D true; + cpu->accel =3D vcpu; + max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); + qemu_add_vm_change_state_handler(whpx_cpu_update_state, env); + + env->aarch64 =3D true; + + /* Allocate enough space for our sysreg sync */ + arm_cpu->cpreg_indexes =3D g_renew(uint64_t, arm_cpu->cpreg_indexes, + sregs_match_len); + arm_cpu->cpreg_values =3D g_renew(uint64_t, arm_cpu->cpreg_values, + sregs_match_len); + arm_cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_indexe= s, + sregs_match_len); + arm_cpu->cpreg_vmstate_values =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_values, + sregs_match_len); + + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); + + /* Populate cp list for all known sysregs */ + for (i =3D 0; i < sregs_match_len; i++) { + const ARMCPRegInfo *ri; + uint32_t key =3D whpx_sreg_match[i].key; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, key); + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + whpx_sreg_match[i].cp_idx =3D sregs_cnt; + arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + } else { + whpx_sreg_match[i].cp_idx =3D -1; + } + } + arm_cpu->cpreg_array_len =3D sregs_cnt; + arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; + + assert(write_cpustate_to_list(arm_cpu, false)); + + /* Set CP_NO_RAW system registers on init */ + val.Reg64 =3D arm_cpu->midr; + whpx_set_reg(cpu, WHvArm64RegisterMidrEl1, + val); + + clean_whv_register_value(&val); + + val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); + whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); + + return 0; + +error: + g_free(vcpu); + + return ret; + +} + +void whpx_cpu_instance_init(CPUState *cs) +{ +} + +int whpx_accel_init(AccelState *as, MachineState *ms) +{ + struct whpx_state *whpx; + int ret; + HRESULT hr; + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + WHV_PARTITION_PROPERTY prop; + WHV_CAPABILITY_FEATURES features =3D {0}; + + whpx =3D &whpx_global; + /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ + whpx->kernel_irqchip =3D true; + + if (!init_whp_dispatch()) { + ret =3D -ENOSYS; + goto error; + } + + whpx->mem_quota =3D ms->ram_size; + + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeHypervisorPresent, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr) || !whpx_cap.HypervisorPresent) { + error_report("WHPX: No accelerator found, hr=3D%08lx", hr); + ret =3D -ENOSPC; + goto error; + } + + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeFeatures, &features, sizeof(features), NULL); + if (FAILED(hr)) { + error_report("WHPX: Failed to query capabilities, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + if (!features.Arm64Support) { + error_report("WHPX: host OS exposing pre-release WHPX implementati= on. " + "Please update your operating system to at least build 26100.3= 915"); + ret =3D -EINVAL; + goto error; + } + + hr =3D whp_dispatch.WHvCreatePartition(&whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to create partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + prop.ProcessorCount =3D ms->smp.cpus; + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeProcessorCount, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition processor count to %u," + " hr=3D%08lx", prop.ProcessorCount, hr); + ret =3D -EINVAL; + goto error; + } + + if (!whpx->kernel_irqchip_allowed) { + error_report("WHPX: on Arm, only kernel-irqchip=3Don is currently = supported"); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + whpx_memory_init(); + + return 0; + +error: + + if (NULL !=3D whpx->partition) { + whp_dispatch.WHvDeletePartition(whpx->partition); + whpx->partition =3D NULL; + } + + return ret; +} --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695416; cv=none; d=zohomail.com; s=zohoarc; b=k86yxYZ4S5Kj1Toimywh0xHRyxcmC6vA3I5rrKG+xG8nBZ1pAm7nYHM9c6RXR9UdM5TWb3VBbqF5jbFWAoQb0qkKVqPsF6MFjO0nFxpBeEQNxExJTEWABbMx/TQHDJPosrVQLfNf4NHy9ykrIx3QsxXeG/Fh7HpSNci2xw8hcho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761695416; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.221; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695422841158500 Content-Type: text/plain; charset="utf-8" This allows edk2 to work on Arm, although u-boot is still not functional. Signed-off-by: Mohamed Mediouni --- accel/whpx/whpx-common.c | 101 +++++++++++++++------------------------ 1 file changed, 38 insertions(+), 63 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c69792e638..aefec4bc8f 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -258,89 +258,64 @@ void whpx_vcpu_kick(CPUState *cpu) * Memory support. */ =20 -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) +static void whpx_set_phys_mem(MemoryRegionSection *section, bool add) { struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); - } - */ - - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { - hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); - } - - if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + MemoryRegion *area =3D section->mr; + bool writable =3D !area->readonly && !area->rom_device; + WHV_MAP_GPA_RANGE_FLAGS flags; + uint64_t page_size =3D qemu_real_host_page_size(); + uint64_t gva =3D section->offset_within_address_space; + uint64_t size =3D int128_get64(section->size); + HRESULT res; + void *mem; + + if (!memory_region_is_ram(area)) { + if (writable) { + return; + } else if (!memory_region_is_romd(area)) { + add =3D false; + } } -} - -static void whpx_process_section(MemoryRegionSection *section, int add) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; =20 - if (!memory_region_is_ram(mr)) { - return; + if (!QEMU_IS_ALIGNED(size, page_size) || + !QEMU_IS_ALIGNED(gva, page_size)) { + /* Not page aligned, so we can not map as RAM */ + add =3D false; } =20 - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { + if (!add) { + res =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, + gva, size); + if (!SUCCEEDED(res)) { + error_report("WHPX: failed to unmap GPA range"); + abort(); + } return; } =20 - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; + flags =3D WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute + | (writable ? WHvMapGpaRangeFlagWrite : 0); + mem =3D memory_region_get_ram_ptr(area) + section->offset_within_regio= n; =20 - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); + res =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + mem, gva, size, flags); + if (!SUCCEEDED(res)) { + error_report("WHPX: failed to map GPA range"); + abort(); + } } =20 static void whpx_region_add(MemoryListener *listener, MemoryRegionSection *section) { - memory_region_ref(section->mr); - whpx_process_section(section, 1); + whpx_set_phys_mem(section, true); } =20 static void whpx_region_del(MemoryListener *listener, MemoryRegionSection *section) { - whpx_process_section(section, 0); - memory_region_unref(section->mr); + whpx_set_phys_mem(section, false); } =20 static void whpx_transaction_begin(MemoryListener *listener) --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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charset="utf-8" Hyper-V supports PSCI 1.3, and that implementation is exposed through WHPX. Signed-off-by: Mohamed Mediouni Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2fc17eab6..854b46f40a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "system/whpx.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1143,6 +1144,8 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled() || hvf_enabled()) { /* TCG and HVF implement PSCI 1.1 */ cpu->psci_version =3D QEMU_PSCI_VERSION_1_1; + } else if (whpx_enabled()) { + cpu->psci_version =3D QEMU_PSCI_VERSION_1_3; } } =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Switch its to a tristate. Windows Hypervisor Platform's vGIC doesn't support ITS. Deal with this by reporting to the user and exiting. Regular configuration: GICv3 + ITS New default configuration with WHPX: GICv3 with GICv2m And its=3Doff explicitly for the newest machine version: GICv3 + GICv2m Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 15 +++++++------ hw/arm/virt.c | 46 +++++++++++++++++++++++++++++++--------- include/hw/arm/virt.h | 4 +++- 3 files changed, 47 insertions(+), 18 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0a6ec74aa0..8e730731ca 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -472,7 +472,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -483,7 +483,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc_mapping_count +=3D rc_its_idmaps->len; } } else { - if (vms->its) { + if (virt_is_its_enabled(vms)) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -498,7 +498,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -517,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -610,7 +610,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. @@ -945,7 +945,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -961,7 +961,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) && !vms->n= o_gicv3_with_gicv2m) { + if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(= vms)) + && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9121eb37eb..dbf9a28b8d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -735,7 +735,7 @@ static void create_its(VirtMachineState *vms) { DeviceState *dev; =20 - assert(vms->its); + assert(virt_is_its_enabled(vms)); if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { /* * Do nothing if ITS is neither supported by the host nor emulated= by @@ -744,6 +744,15 @@ static void create_its(VirtMachineState *vms) return; } =20 + if (whpx_enabled() && vms->tcg_its) { + /* + * Signal to the user when ITS is neither supported by the host + * nor emulated by the machine. + */ + info_report("ITS not supported on WHPX."); + exit(1); + } + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), @@ -955,7 +964,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(vm= s)) { create_its(vms); } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { create_v2m(vms); @@ -2705,18 +2714,34 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 -static bool virt_get_its(Object *obj, Error **errp) +bool virt_is_its_enabled(VirtMachineState *vms) +{ + if (vms->its =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + if (vms->its =3D=3D ON_OFF_AUTO_AUTO) { + if (whpx_enabled()) { + return false; + } + } + return true; +} + +static void virt_get_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); + OnOffAuto its =3D vms->its; =20 - return vms->its; + visit_type_OnOffAuto(v, name, &its, errp); } =20 -static void virt_set_its(Object *obj, bool value, Error **errp) +static void virt_set_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - vms->its =3D value; + visit_type_OnOffAuto(v, name, &vms->its, errp); } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3426,8 +3451,9 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 - object_class_property_add_bool(oc, "its", virt_get_its, - virt_set_its); + object_class_property_add(oc, "its", "OnOffAuto", + virt_get_its, virt_set_its, + NULL, NULL); object_class_property_set_description(oc, "its", "Set on/off to enable/disable " "ITS instantiation"); @@ -3487,8 +3513,8 @@ static void virt_instance_init(Object *obj) vms->highmem_mmio =3D true; vms->highmem_redists =3D true; =20 - /* Default allows ITS instantiation */ - vms->its =3D true; + /* Default allows ITS instantiation if available */ + vms->its =3D ON_OFF_AUTO_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; vms->no_gicv3_with_gicv2m =3D false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d31348dd61..997dd51678 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -149,7 +149,7 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; - bool its; + OnOffAuto its; bool tcg_its; bool virt; bool ras; @@ -218,4 +218,6 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +bool virt_is_its_enabled(VirtMachineState *vms); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.89.203; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695819062158500 Content-Type: text/plain; charset="utf-8" Introduce a -M msi=3D argument to be able to control MSI-X support independ= ently from ITS, as part of supporting GICv3 + GICv2m platforms. Remove vms->its as it's no longer needed after that change. Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 3 +- hw/arm/virt.c | 110 +++++++++++++++++++++++++++++++-------- include/hw/arm/virt.h | 4 +- 3 files changed, 93 insertions(+), 24 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 8e730731ca..a6a56455a9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -961,8 +961,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(= vms)) - && !vms->no_gicv3_with_gicv2m) { + if (virt_is_gicv2m_enabled(vms)) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index dbf9a28b8d..6978d4e867 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -964,12 +964,12 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(vm= s)) { + if (virt_is_its_enabled(vms)) { create_its(vms); - } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { - create_v2m(vms); - } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + } else if (virt_is_gicv2m_enabled(vms)) { create_v2m(vms); + } else { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; } } =20 @@ -2716,32 +2716,93 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, =20 bool virt_is_its_enabled(VirtMachineState *vms) { - if (vms->its =3D=3D ON_OFF_AUTO_OFF) { - return false; + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + return false; + case VIRT_MSI_CTRL_ITS: + return true; + case VIRT_MSI_CTRL_GICV2M: + return false; + case VIRT_MSI_CTRL_AUTO: + if (whpx_enabled() && whpx_irqchip_in_kernel()) { + return false; + } + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + return false; + } + return true; + default: + return false; } - if (vms->its =3D=3D ON_OFF_AUTO_AUTO) { - if (whpx_enabled()) { +} + +bool virt_is_gicv2m_enabled(VirtMachineState *vms) +{ + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: return false; - } + default: + return !virt_is_its_enabled(vms); } - return true; } =20 -static void virt_get_its(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static char *virt_get_msi(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + const char *val; + + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + val =3D "off"; + break; + case VIRT_MSI_CTRL_ITS: + val =3D "its"; + break; + case VIRT_MSI_CTRL_GICV2M: + val =3D "gicv2m"; + default: + val =3D "auto"; + break; + } + return g_strdup(val); +} + +static void virt_set_msi(Object *obj, const char *value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); - OnOffAuto its =3D vms->its; =20 - visit_type_OnOffAuto(v, name, &its, errp); + if (!strcmp(value, "auto")) { + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Will be overriden l= ater */ + } else if (!strcmp(value, "its")) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else if (!strcmp(value, "gicv2m")) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (!strcmp(value, "none")) { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } else { + error_setg(errp, "Invalid msi value"); + error_append_hint(errp, "Valid values are auto, gicv2m, its, off\n= "); + } } =20 -static void virt_set_its(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static bool virt_get_its(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - visit_type_OnOffAuto(v, name, &vms->its, errp); + return virt_is_its_enabled(vms); +} + +static void virt_set_its(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + if (value) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else if (vms->no_gicv3_with_gicv2m) { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } else { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3068,6 +3129,8 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, db_start =3D base_memmap[VIRT_GIC_V2M].base; db_end =3D db_start + base_memmap[VIRT_GIC_V2M].size - 1; break; + case VIRT_MSI_CTRL_AUTO: + g_assert_not_reached(); } resv_prop_str =3D g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", db_start, db_end, @@ -3451,13 +3514,18 @@ static void virt_machine_class_init(ObjectClass *oc= , const void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 - object_class_property_add(oc, "its", "OnOffAuto", - virt_get_its, virt_set_its, - NULL, NULL); + object_class_property_add_bool(oc, "its", virt_get_its, + virt_set_its); object_class_property_set_description(oc, "its", "Set on/off to enable/disable " "ITS instantiation"); =20 + object_class_property_add_str(oc, "msi", virt_get_msi, + virt_set_msi); + object_class_property_set_description(oc, "msi", + "Set MSI settings. " + "Valid values are auto/gicv2m/it= s/off"); + object_class_property_add_bool(oc, "dtb-randomness", virt_get_dtb_randomness, virt_set_dtb_randomness); @@ -3514,7 +3582,7 @@ static void virt_instance_init(Object *obj) vms->highmem_redists =3D true; =20 /* Default allows ITS instantiation if available */ - vms->its =3D ON_OFF_AUTO_AUTO; + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; vms->no_gicv3_with_gicv2m =3D false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 997dd51678..99db8607e7 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -101,6 +101,8 @@ typedef enum VirtIOMMUType { =20 typedef enum VirtMSIControllerType { VIRT_MSI_CTRL_NONE, + /* This value is overriden at runtime.*/ + VIRT_MSI_CTRL_AUTO, VIRT_MSI_CTRL_GICV2M, VIRT_MSI_CTRL_ITS, } VirtMSIControllerType; @@ -149,7 +151,6 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; 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charset="utf-8" Looks like in the prior Qemu ACPI table handling, GICv2 configurations had vms->its=3D1... Match that assumption to not make the test suite fail. Probably not merge-w= orthy... And then maybe see what to do for older releases too? Signed-off-by: Mohamed Mediouni --- hw/arm/virt-acpi-build.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a6a56455a9..39dd3d1020 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -472,7 +472,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (virt_is_its_enabled(vms)) { + if (virt_is_its_enabled(vms) || vms->gic_version =3D=3D 2) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -483,7 +483,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc_mapping_count +=3D rc_its_idmaps->len; } } else { - if (virt_is_its_enabled(vms)) { + if (virt_is_its_enabled(vms) || vms->gic_version =3D=3D 2) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -498,7 +498,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (virt_is_its_enabled(vms)) { + if (virt_is_its_enabled(vms) || vms->gic_version =3D=3D 2) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -517,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (virt_is_its_enabled(vms)) { + if (virt_is_its_enabled(vms) || vms->gic_version =3D=3D 2) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -610,7 +610,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (virt_is_its_enabled(vms)) { + if (virt_is_its_enabled(vms) || vms->gic_version =3D=3D 2) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Update the documentation to match current QEMU. Remove the mention of pre-2.7 machine models as those aren't provided anymore. Signed-off-by: Mohamed Mediouni --- docs/system/arm/virt.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 10cbffc8a7..fe95be991e 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -40,9 +40,10 @@ The virt board supports: - An optional SMMUv3 IOMMU - hotpluggable DIMMs - hotpluggable NVDIMMs -- An MSI controller (GICv2M or ITS). GICv2M is selected by default along - with GICv2. ITS is selected by default with GICv3 (>=3D virt-2.7). Note - that ITS is not modeled in TCG mode. +- An MSI controller (GICv2m or ITS). + - When using a GICv3, ITS is selected by default when available on the p= latform. + - If using a GICv2 or when ITS is not available, a GICv2m is provided by= default instead. + - Before virt-10.2, a GICv2m is not provided when the ITS is disabled. - 32 virtio-mmio transport devices - running guests using the KVM accelerator on aarch64 hardware - large amounts of RAM (at least 255GB, and more if using highmem) @@ -167,8 +168,7 @@ gic-version ``4`` if ``virtualization`` is ``on``, but this may change in future) =20 its - Set ``on``/``off`` to enable/disable ITS instantiation. The default is `= `on`` - for machine types later than ``virt-2.7``. + Set ``on``/``off``/``auto`` to control ITS instantiation. The default is= ``auto``. =20 iommu Set the IOMMU type to create for the guest. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.182; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695494352154100 Content-Type: text/plain; charset="utf-8" Code taken from HVF and adapted for WHPX use. Note that WHPX doesn't have a default vs maximum IPA distinction. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 32 ++++++++++++++++++++++++++ include/hw/boards.h | 1 + target/arm/whpx/meson.build | 2 ++ target/arm/whpx/whpx-all.c | 45 +++++++++++++++++++++++++++++++++++++ target/arm/whpx/whpx-stub.c | 15 +++++++++++++ target/arm/whpx_arm.h | 16 +++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 target/arm/whpx/whpx-stub.c create mode 100644 target/arm/whpx_arm.h diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6978d4e867..480d165ebc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -70,6 +70,7 @@ #include "hw/irq.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "hw/firmware/smbios.h" #include "qapi/visitor.h" #include "qapi/qapi-visit-common.h" @@ -3316,6 +3317,36 @@ static int virt_kvm_type(MachineState *ms, const cha= r *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 +static int virt_whpx_get_physical_address_range(MachineState *ms) +{ + VirtMachineState *vms =3D VIRT_MACHINE(ms); + + int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); + + /* We freeze the memory map to compute the highest gpa */ + virt_set_memmap(vms, max_ipa_size); + + int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); + + /* + * If we're <=3D the default IPA size just use the default. + * If we're above the default but below the maximum, round up to + * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only + * returns values that are valid ARM PARange values. + */ + if (requested_ipa_size <=3D max_ipa_size) { + requested_ipa_size =3D max_ipa_size; + } else { + error_report("-m and ,maxmem option values " + "require an IPA range (%d bits) larger than " + "the one supported by the host (%d bits)", + requested_ipa_size, max_ipa_size); + return -1; + } + + return requested_ipa_size; +} + static int virt_hvf_get_physical_address_range(MachineState *ms) { VirtMachineState *vms =3D VIRT_MACHINE(ms); @@ -3408,6 +3439,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; + mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/boards.h b/include/hw/boards.h index a48ed4f86a..fb2c531018 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -278,6 +278,7 @@ struct MachineClass { void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); int (*hvf_get_physical_address_range)(MachineState *machine); + int (*whpx_get_physical_address_range)(MachineState *machine); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build index 1de2ef0283..3df632c9d3 100644 --- a/target/arm/whpx/meson.build +++ b/target/arm/whpx/meson.build @@ -1,3 +1,5 @@ arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', )) + +arm_common_system_ss.add(when: 'CONFIG_WHPX', if_false: files('whpx-stub.c= ')) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 8c34650765..e6bafb0601 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -35,6 +35,7 @@ #include "system/whpx-accel-ops.h" #include "system/whpx-all.h" #include "system/whpx-common.h" +#include "whpx_arm.h" #include "hw/arm/bsa.h" #include "arm-powerctl.h" =20 @@ -657,6 +658,40 @@ static void whpx_cpu_update_state(void *opaque, bool r= unning, RunState state) { } =20 +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + HRESULT hr; + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodePhysicalAddressWidth, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr)) { + error_report("WHPX: failed to get supported" + "physical address width, hr=3D%08lx", hr); + } + + /* + * We clamp any IPA size we want to back the VM with to a valid PARange + * value so the guest doesn't try and map memory outside of the valid = range. + * This logic just clamps the passed in IPA bit size to the first valid + * PARange value <=3D to it. + */ + return round_down_to_parange_bit_size(whpx_cap.PhysicalAddressWidth); +} + +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) +{ + uint32_t ipa_size =3D whpx_arm_get_ipa_bit_size(); + uint64_t id_aa64mmfr0; + + /* Clamp down the PARange to the IPA size the kernel supports. */ + uint8_t index =3D round_down_to_parange_index(ipa_size); + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; @@ -735,6 +770,7 @@ int whpx_init_vcpu(CPUState *cpu) val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); =20 + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); return 0; =20 error: @@ -757,6 +793,8 @@ int whpx_accel_init(AccelState *as, MachineState *ms) UINT32 whpx_cap_size; WHV_PARTITION_PROPERTY prop; WHV_CAPABILITY_FEATURES features =3D {0}; + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + int pa_range =3D 0; =20 whpx =3D &whpx_global; /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ @@ -767,6 +805,13 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + if (mc->whpx_get_physical_address_range) { + pa_range =3D mc->whpx_get_physical_address_range(ms); + if (pa_range < 0) { + return -EINVAL; + } + } + whpx->mem_quota =3D ms->ram_size; =20 hr =3D whp_dispatch.WHvGetCapability( diff --git a/target/arm/whpx/whpx-stub.c b/target/arm/whpx/whpx-stub.c new file mode 100644 index 0000000000..32e434a5f6 --- /dev/null +++ b/target/arm/whpx/whpx-stub.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WHPX stubs for ARM + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "whpx_arm.h" + +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + g_assert_not_reached(); +} diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h new file mode 100644 index 0000000000..de7406b66f --- /dev/null +++ b/target/arm/whpx_arm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WHPX support -- ARM specifics + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#ifndef QEMU_WHPX_ARM_H +#define QEMU_WHPX_ARM_H + +#include "target/arm/cpu-qom.h" + +uint32_t whpx_arm_get_ipa_bit_size(void); + +#endif --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695922; cv=none; d=zohomail.com; s=zohoarc; b=mOS/Ae5g4IxS7geVdq0wGjZQS1tUQPJjBl9Acz7QzWyFnKpGlpUDIRhWWWjnkRIGOafohkFQdWIXaw+eL5/bi9kFX0npyQJwesQ5sx4/YUTczYoiMe2sQTRNueDJXfY8xhPIyUxCMzVj2Abd12B1SDyXCNLCJy++y06U2vRvuYY= ARC-Message-Signature: i=1; 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s=sig1; bh=2LnAPGX4HuFpDCVnU0NG6yresAdDa/+GNcrH6VwGz6k=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=ekd9FnRVGP2nhLxHLAbJl3W6S2+ptUNz8/3Pk05AWImizdALG6cHCN5LoVj0WHZZUMJjxGDU12Nbee3loFD/9i9XiOVtSUNPqd6b9AvD56hY9Ad3/SLg5WALcB7Wp7C1MWCJnMoWPR8UGnlFr9pwZLxD6uSkhRjmjHOAnBLy9+XoC1s1FZI0n7r5Mbtth9CRbKgMQpaUZ371PSiq/ND7Mg0MHFs2ZrCNzFDpn0L6f/lVsOKXpbX7SNDRkImmPmS+dZRVBArGML6JFG/iRSPXx1I3JDN6df8GiBU3lDcKZb6retX3YAPicMuYMq4Dsm1A3dfeRDUjBn0ABWTlpBVi7w== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: mohamed@unpredictable.fr, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Phil Dennis-Jordan , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Richard Henderson , Pedro Barbuda , Pierrick Bouvier Subject: [PATCH v9 20/27] hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF Date: Wed, 29 Oct 2025 00:47:50 +0100 Message-ID: <20251028234757.39609-21-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251028234757.39609-1-mohamed@unpredictable.fr> References: <20251028234757.39609-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: H_rqGxZ96ueDSjB1GTMrqSVTZHdyMyeT X-Proofpoint-GUID: H_rqGxZ96ueDSjB1GTMrqSVTZHdyMyeT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDIwMiBTYWx0ZWRfX29swaxWCAQKG 2S90lbuFH/Po1WASqZi7FsgfDZdVajgWoWKDHfZUjau1FQcjzNzQeecDHUd9IO8ZAP6SNcKxoz5 1dXTmmDgTI1oRYXbnJJmZrlnJPqszPCEWZdaMa6x9f4+YtLpvzi6jN06YILVy0r6fzylgSJ/sAj I4EXcadn7SEBbDLw/s3SRQOdi14qZR5Qj7wkZxkBrf2NTeqfb18cUewuk14WSF+3NlOKfC/6Kab NVw3IXURk6UrJg9RbMTUaVC4HvDNMLdcqzw9MMt6tUUj8zIkAzsOeFP46OH++S0chAAq/ge1U= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_09,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 adultscore=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510280202 X-JNJ: AAAAAAABcbpnk/kvcdAV8LOzJSgW6Vru9OBuAKT8ezlDcWouSv+n/XFa3Qdb3XVG95XFFM01Xg2yE0hcv2BXBVPUfNNzrwCcfc8YRdXPbWUgGqjnbFEldzhXQo63z8fM+ILX960wDzzMeeY8hRzHDgmiuJSkbZe4pVUR3BRtP+C4G5vZtHucxkeoR1BbbbZlkiErFrG4CdybOBKbD9Z4hym5QNQHu0VYZ97xWSX0jJPhdG7JnD8cV5wr0PtMJJXZbnTG9vnMhG4whA9TMyU6ZT96jJHv05pqunPGT2i5UoizWCow0ERCzh97A2tj9PBQ55dbROqmSaCE3hJMleljR9uS1or5VMpKnlN9oePKnyqIXMWSqvNs87IQsDfx29cc1jnCbCw9lxFfr/vGD53OiY2MLRmSZ29qASx+VKfiiTowSoFDHixh7bEGERHOoBE4tlcGjZhIhObQZXWGEIJkpkbktJY8iEKiZMBZvxrQfMuAi3EnpLvl3a7FXbu/yixLlcyq4gf28etQcWtLbKfRt8pjtylRL1cMky7d7Hi7cpiZdIXoqq4BM7iOeJqNtV2kCaHBs1rIAEeJWt5CdWph51nKdLy5GInXfBOl8gYnthFgEnMdvSYNrqHExTUdoa7aBPJmeG7Ihmrkgn8Z4O2vNRJ2LMBHYg0ELEcafLVyWOOTTosPX5gO7ZDO3IRpE8N03VSXfAhCHbjDx+yLqgtIHc+J65PFbh9yBfLYt8flEoiRFcn3cxm7MK2gBfan4wJwtlc/8kceT4Q4W2Dqzt08g2oXpcBLHYFmk//ivpdb8LxhLGhhYPZdZ7VaFTevs6DC67gRbnA= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.176; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695926229158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/hvf/hvf-all.c | 7 +++++-- hw/arm/virt.c | 41 ++++---------------------------------- include/hw/boards.h | 4 ++-- include/system/hvf_int.h | 2 ++ target/arm/hvf-stub.c | 20 ------------------- target/arm/hvf/hvf.c | 6 +++--- target/arm/hvf_arm.h | 3 --- target/arm/meson.build | 1 - target/arm/whpx/whpx-all.c | 5 +++-- target/i386/hvf/hvf.c | 11 ++++++++++ 10 files changed, 30 insertions(+), 70 deletions(-) delete mode 100644 target/arm/hvf-stub.c diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0a4b498e83..8229ad8640 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -17,6 +17,7 @@ #include "system/hvf_int.h" #include "hw/core/cpu.h" #include "hw/boards.h" +#include "target/arm/hvf_arm.h" #include "trace.h" =20 bool hvf_allowed; @@ -256,8 +257,10 @@ static int hvf_accel_init(AccelState *as, MachineState= *ms) int pa_range =3D 36; MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - if (mc->hvf_get_physical_address_range) { - pa_range =3D mc->hvf_get_physical_address_range(ms); + + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + hvf_arch_get_default_ipa_bit_size(), hvf_arch_get_max_ipa_bit_= size()); if (pa_range < 0) { return -EINVAL; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 480d165ebc..58fa657cae 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3317,43 +3317,11 @@ static int virt_kvm_type(MachineState *ms, const ch= ar *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 -static int virt_whpx_get_physical_address_range(MachineState *ms) +static int virt_get_physical_address_range(MachineState *ms, + int default_ipa_size, int max_ipa_size) { VirtMachineState *vms =3D VIRT_MACHINE(ms); =20 - int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); - - /* We freeze the memory map to compute the highest gpa */ - virt_set_memmap(vms, max_ipa_size); - - int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); - - /* - * If we're <=3D the default IPA size just use the default. - * If we're above the default but below the maximum, round up to - * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only - * returns values that are valid ARM PARange values. - */ - if (requested_ipa_size <=3D max_ipa_size) { - requested_ipa_size =3D max_ipa_size; - } else { - error_report("-m and ,maxmem option values " - "require an IPA range (%d bits) larger than " - "the one supported by the host (%d bits)", - requested_ipa_size, max_ipa_size); - return -1; - } - - return requested_ipa_size; -} - -static int virt_hvf_get_physical_address_range(MachineState *ms) -{ - VirtMachineState *vms =3D VIRT_MACHINE(ms); - - int default_ipa_size =3D hvf_arm_get_default_ipa_bit_size(); - int max_ipa_size =3D hvf_arm_get_max_ipa_bit_size(); - /* We freeze the memory map to compute the highest gpa */ virt_set_memmap(vms, max_ipa_size); =20 @@ -3362,7 +3330,7 @@ static int virt_hvf_get_physical_address_range(Machin= eState *ms) /* * If we're <=3D the default IPA size just use the default. * If we're above the default but below the maximum, round up to - * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only + * the maximum. hvf_arch_get_max_ipa_bit_size() conveniently only * returns values that are valid ARM PARange values. */ if (requested_ipa_size <=3D default_ipa_size) { @@ -3438,8 +3406,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->valid_cpu_types =3D valid_cpu_types; mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; - mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; - mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; + mc->get_physical_address_range =3D virt_get_physical_address_range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/boards.h b/include/hw/boards.h index fb2c531018..fa5f71471d 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -277,8 +277,8 @@ struct MachineClass { void (*reset)(MachineState *state, ResetType type); void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); - int (*hvf_get_physical_address_range)(MachineState *machine); - int (*whpx_get_physical_address_range)(MachineState *machine); + int (*get_physical_address_range)(MachineState *machine, + int default_ipa_size, int max_ipa_size); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index a3b06a3e75..8b6447c238 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -71,6 +71,8 @@ void assert_hvf_ok_impl(hv_return_t ret, const char *file= , unsigned int line, const char *hvf_return_string(hv_return_t ret); int hvf_arch_init(void); hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); +uint32_t hvf_arch_get_default_ipa_bit_size(void); +uint32_t hvf_arch_get_max_ipa_bit_size(void); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); int hvf_vcpu_exec(CPUState *); diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c deleted file mode 100644 index ff137267a0..0000000000 --- a/target/arm/hvf-stub.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * QEMU Hypervisor.framework (HVF) stubs for ARM - * - * Copyright (c) Linaro - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include "qemu/osdep.h" -#include "hvf_arm.h" - -uint32_t hvf_arm_get_default_ipa_bit_size(void) -{ - g_assert_not_reached(); -} - -uint32_t hvf_arm_get_max_ipa_bit_size(void) -{ - g_assert_not_reached(); -} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0658a99a2d..ecca1a63ec 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -725,7 +725,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? - chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + chosen_ipa_bit_size : hvf_arch_get_max_ipa_bit_size(); uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ @@ -816,7 +816,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) return r =3D=3D HV_SUCCESS; } =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void) +uint32_t hvf_arch_get_default_ipa_bit_size(void) { uint32_t default_ipa_size; hv_return_t ret =3D hv_vm_config_get_default_ipa_size(&default_ipa_siz= e); @@ -825,7 +825,7 @@ uint32_t hvf_arm_get_default_ipa_bit_size(void) return default_ipa_size; } =20 -uint32_t hvf_arm_get_max_ipa_bit_size(void) +uint32_t hvf_arch_get_max_ipa_bit_size(void) { uint32_t max_ipa_size; hv_return_t ret =3D hv_vm_config_get_max_ipa_size(&max_ipa_size); diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..5d19d82e5d 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -22,7 +22,4 @@ void hvf_arm_init_debug(void); =20 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void); -uint32_t hvf_arm_get_max_ipa_bit_size(void); - #endif diff --git a/target/arm/meson.build b/target/arm/meson.build index 61277a627c..9f2eb91635 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -41,7 +41,6 @@ arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) arm_common_system_ss.add(files( diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index e6bafb0601..23c7beefaf 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -805,8 +805,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - if (mc->whpx_get_physical_address_range) { - pa_range =3D mc->whpx_get_physical_address_range(ms); + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + whpx_arm_get_ipa_bit_size(), whpx_arm_get_ipa_bit_size()); if (pa_range < 0) { return -EINVAL; } diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 33f723a76a..1d7ec47f59 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -225,6 +225,17 @@ int hvf_arch_init(void) return 0; } =20 +/* 48-bit on all Intel Macs. Function currently unused. */ +uint32_t hvf_arch_get_default_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + +uint32_t hvf_arch_get_max_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) { return hv_vm_create(HV_VM_DEFAULT); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695754; cv=none; d=zohomail.com; s=zohoarc; b=OUpn45YirCaphL0WdCN4cvDehwdEbZK2TD0DEvJdojGPI2pzVGoup1dOTK51CXgH7+4NqsXJC+k8IInhFBxHR58cTIgpe9QkeRBba7FomIRUo0pwpFO76IdsMOfptgq19oadK13PXqR3Rjbjo0W5jppKQ3evjbswUeL6hSOZ3CM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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s=sig1; bh=UOGHA4PGi6Sk/oKzT0z+MFnVyAcKEZbG5DcuwsP+3fI=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=WG3vCYhTIYf8JP/dVJUIN3u04JMyIfMZxpURWAEnsQ6rA53rMXO1Z2vML5jqAPo9WoMnmjNwwj340HeryBZTn0g0ldHRBLLhbqyrq4KNI3ZYCO13xQ2nOm7NvFU+S0OILk1uDHlADmi3/Esul8e+FQyQkgJ4d1kQsVjBlIbbkoSCxBapDyXrsIGu69MMj+57ikXK2KjUwsHQMu0tFLkT82CTO3r7Wj4q/AYBCyB4W7edf5VQNzWUxXe746laOrKmZBp+3DS5beo3VKIsw8cAAzNKVu492DjPjKYvSGCwIpD8TDb2lOv0ZX1gxcFxkZaKttlOkrNT3ry6fm6/Q4w3iw== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: mohamed@unpredictable.fr, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Phil Dennis-Jordan , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Richard Henderson , Pedro Barbuda , Pierrick Bouvier Subject: [PATCH v9 21/27] whpx: arm64: implement -cpu host Date: Wed, 29 Oct 2025 00:47:51 +0100 Message-ID: <20251028234757.39609-22-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251028234757.39609-1-mohamed@unpredictable.fr> References: <20251028234757.39609-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: iZz5opAJkUqQFLXHySvwDjwBOCqEvh85 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDIwMiBTYWx0ZWRfX0s0zy6uJ2pqv zQU9gWF03MgOhajtI4/hJmg+VRZ2O6mXZNw/NP7oqeJ4Moohd5knb8qTnadkuZF78S0yL6JjfbM iB9V0bIruaQ+EKJSZiYXkY8PxOLLOwzMrrRfRQ0ZyCeTzqsr/AAGyMmUSwtzXPOSGnTUCRk/nIr UbXknZ3qbAlSHc+TLuDxdBJQEWKAae+GsL/taaoXXxMU4hjhRGPBgT3dQGln3fbjRgO/0SYvsr5 /eHXEqoPMzMkeB2+z+4ZG0ND8trBHlJVRcZIRLeG/38sSJqr9X9joX/01rWcZxpSNa6EV93go= X-Proofpoint-ORIG-GUID: iZz5opAJkUqQFLXHySvwDjwBOCqEvh85 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_09,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 spamscore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 clxscore=1030 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510280202 X-JNJ: AAAAAAABp9OggUpeh50Ds+jIVMjNm27krG7uU7N7VvK5qIA35IVA8K0XMJDF6KbtjqVsC2xpqd9mqmsfsidMqIHII5WjL4xPIgGYBZOKfuEEtz/vcgPfbvS+xacdtB2yuJcItpy3Y/F2SUBa0Lfb7LXnBsntE78bwePrKUIGkgnpsNidtpwgwuvjsD9dhzbDW26zzuwHICCY3ivOp7cSUx+5uvnJlUxJZ5jVJiw25L/QywzU707Njqiq2njvXVhTnATCH6jRdyAJ9viESPlMTlmJ3tLREgU8r5m0HxhyTVmYO6/SZz8lPI2ejJV9QypJtWnkLl2pRa2rWWzrIrIMNuXN+Tpsx3cdIbYiLtjKW+WY7uKp5JAv8Kjyhl8NhlcICNQImNXgOlaNh3iSHzMIuzbqLN2qBo9EPHlrm8DHELmwdWPzSCq4+tujpqfTdbPlu3BtBq5FXWMOl2VlMrXbB8TTjfRx1GTBjIYj87FUIkrK4xttOLJqonWleGJu/hRB2hOjr5VfSlbLwcZuvU71C1ob2erp7km12IUFQnR2bfjZQgGjXS/IH642e+jhSfvRePMtzdTH+EJpAHEkz8U4o1iNwg1DEXg1y/g8dLQBeZjNJ+YSguwQbT41tY+OAdMKASz4Ime77Xxnyt+3qDCRYqUF+Dyc3ZJqt7cKfyr7RJZK2AU2w3a7VTI0Hj0ETBqQWvIyywtt4mDfIaEjPEpfcZcnm24pq6X+25TWVjKyN3S1WRkn+0VsrLbbMyVje7JFeIMR5n0= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.153; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695755086154100 Content-Type: text/plain; charset="utf-8" Logic to fetch MIDR_EL1 for cpu 0 adapted from: https://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c7= 4/Source/Windows/Common/CPUFeatures.cpp#L62 Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 2 +- target/arm/cpu64.c | 19 ++++--- target/arm/whpx/whpx-all.c | 104 +++++++++++++++++++++++++++++++++++++ target/arm/whpx_arm.h | 1 + 4 files changed, 119 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 58fa657cae..9ec3cf00f5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3371,7 +3371,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) #ifdef TARGET_AARCH64 ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) ARM_CPU_TYPE_NAME("host"), #endif /* CONFIG_KVM || CONFIG_HVF */ #endif /* TARGET_AARCH64 */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 26cf7e6dfa..3f00071081 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,10 +26,13 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "system/hw_accel.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" @@ -522,7 +525,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. * The algorithm selection properties are not present. @@ -599,10 +602,10 @@ void aarch64_add_pauth_properties(Object *obj) =20 /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM or hvf. Is it just a bit backward? Yes it is! + * property for HW accel. Is it just a bit backward? Yes it is! * Note that prop_pauth is true whether the host CPU supports the * architected QARMA5 algorithm or the IMPDEF one. We don't * provide the separate pauth-impdef property for KVM or hvf, @@ -773,6 +776,10 @@ static void aarch64_host_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); aarch64_add_pauth_properties(obj); +#elif defined(CONFIG_WHPX) + ARMCPU *cpu =3D ARM_CPU(obj); + whpx_arm_set_cpu_features_from_host(cpu); + aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); #endif @@ -780,8 +787,8 @@ static void aarch64_host_initfn(Object *obj) =20 static void aarch64_max_initfn(Object *obj) { - if (kvm_enabled() || hvf_enabled()) { - /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ + if (hwaccel_enabled()) { + /* When hardware acceleration enabled, '-cpu max' is identical to = '-cpu host' */ aarch64_host_initfn(obj); return; } @@ -800,7 +807,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) { .name =3D "host", .initfn =3D aarch64_host_initfn }, #endif }; diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 23c7beefaf..8f0a54f080 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -41,6 +41,17 @@ =20 #include #include +#include + +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; =20 struct whpx_reg_match { WHV_REGISTER_NAME reg; @@ -692,6 +703,99 @@ static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARM= ISARegisters *isar) SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 +static uint64_t whpx_read_midr(void) +{ + HKEY key; + uint64_t midr_el1; + DWORD size =3D sizeof(midr_el1); + const char *path =3D "Hardware\\Description\\System\\CentralProcessor\= \0\\"; + assert(!RegOpenKeyExA(HKEY_LOCAL_MACHINE, path, 0, KEY_READ, &key)); + assert(!RegGetValueA(key, NULL, "CP 4000", RRF_RT_REG_QWORD, NULL, &mi= dr_el1, &size)); + RegCloseKey(key); + return midr_el1; +} + +static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + const struct isar_regs { + WHV_REGISTER_NAME reg; + uint64_t *val; + } regs[] =3D { + { WHvArm64RegisterIdAa64Pfr0El1, &ahcf->isar.idregs[ID_AA64PFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Pfr1El1, &ahcf->isar.idregs[ID_AA64PFR1_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr0El1, &ahcf->isar.idregs[ID_AA64DFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr1El1 , &ahcf->isar.idregs[ID_AA64DFR1_E= L1_IDX] }, + { WHvArm64RegisterIdAa64Isar0El1, &ahcf->isar.idregs[ID_AA64ISAR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar1El1, &ahcf->isar.idregs[ID_AA64ISAR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar2El1, &ahcf->isar.idregs[ID_AA64ISAR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] } + }; + + int i; + WHV_REGISTER_VALUE val; + + ahcf->dtb_compatible =3D "arm,armv8"; + ahcf->features =3D (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + for (i =3D 0; i < ARRAY_SIZE(regs); i++) { + clean_whv_register_value(&val); + whpx_get_global_reg(regs[i].reg, &val); + *regs[i].val =3D val.Reg64; + } + + /* + * MIDR_EL1 is not a global register on WHPX + * As such, read the CPU0 from the registry to get a consistent value. + * Otherwise, on heterogenous systems, you'll get variance between CPU= s. + */ + ahcf->midr =3D whpx_read_midr(); + + clamp_id_aa64mmfr0_parange_to_ipa_size(&ahcf->isar); + + /* + * Disable SVE, which is not supported by QEMU whpx yet. + * Work needed for SVE support: + * - SVE state save/restore + * - any potentially needed VL management + * Also disable SME at the same time. (not currently supported by Hype= r-V) + */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, + GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MAS= K); + + SET_IDREG(&ahcf->isar, ID_AA64PFR1, + GET_IDREG(&ahcf->isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MAS= K); + + return true; +} + +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!whpx_enabled() || + !whpx_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed =3D true; + return; + } + } + + cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; + cpu->env.features =3D arm_host_cpu_features.features; + cpu->midr =3D arm_host_cpu_features.midr; + cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h index de7406b66f..df65fd753c 100644 --- a/target/arm/whpx_arm.h +++ b/target/arm/whpx_arm.h @@ -12,5 +12,6 @@ #include "target/arm/cpu-qom.h" =20 uint32_t whpx_arm_get_ipa_bit_size(void); +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 #endif --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695943; cv=none; d=zohomail.com; s=zohoarc; b=VN5GsNzRoxUFnCOHlkOty37VhWShKJbXGvkuCmYgn+foox7Sssw8jrdTuI6AfcH25uEyL0XhWcgxbFaNz0yXdVVC2F4stcttSNaos52XIgxIiV9g5xLWMgDrVEVf2s/Huvn+YINq3glLXnoBGUs17bSsk20FAeMSOBucZuSeb5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761695943; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.160; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695944365158500 Content-Type: text/plain; charset="utf-8" While figuring out a better spot for it, put it in whpx_accel_init. Needs to be done before WHvSetupPartition. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- target/arm/whpx/whpx-all.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 8f0a54f080..4d58e5e939 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -973,6 +973,29 @@ int whpx_accel_init(AccelState *as, MachineState *ms) =20 memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); =20 + WHV_ARM64_IC_PARAMETERS ic_params =3D { + .EmulationMode =3D WHvArm64IcEmulationModeGicV3, + .GicV3Parameters =3D { + .GicdBaseAddress =3D 0x08000000, + .GitsTranslaterBaseAddress =3D 0x08080000, + .GicLpiIntIdBits =3D 0, + .GicPpiPerformanceMonitorsInterrupt =3D VIRTUAL_PMU_IRQ, + .GicPpiOverflowInterruptFromCntv =3D ARCH_TIMER_VIRT_IRQ + } + }; + prop.Arm64IcParameters =3D ic_params; + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeArm64IcParameters, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + if (FAILED(hr)) { + error_report("WHPX: Failed to enable GICv3 interrupt controller, h= r=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); if (FAILED(hr)) { error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695717; cv=none; d=zohomail.com; s=zohoarc; b=CIW2IrZN1vYGJloe6v3ODxaZi6b0xBgx1iwLnlAGusFIzYY1axqbFt7uJWJo96C5SWMEXjkFAXK93FBGBsAcch+JU7OZsuVHoJNBNw/1aQ/rGGTiWhxJe5uHtCHPAEEIqjscNdcL1B5ir//0JdWxulsbo3etaSkNzLNinvw2yT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761695717; 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charset="utf-8" GICv3 state save-restore is currently not implemented yet. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/intc/arm_gicv3_whpx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c index 88a05e5901..6ceae78483 100644 --- a/hw/intc/arm_gicv3_whpx.c +++ b/hw/intc/arm_gicv3_whpx.c @@ -17,6 +17,7 @@ #include "system/whpx-internal.h" #include "gicv3_internal.h" #include "vgic_common.h" +#include "migration/blocker.h" #include "qom/object.h" #include "target/arm/cpregs.h" =20 @@ -205,6 +206,15 @@ static void whpx_gicv3_realize(DeviceState *dev, Error= **errp) error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); return; } + + Error *whpx_migration_blocker =3D NULL; + + error_setg(&whpx_migration_blocker, + "Live migration disabled because GIC state save/restore not suppor= ted on WHPX"); + if (migrate_add_blocker(&whpx_migration_blocker, errp)) { + error_free(whpx_migration_blocker); + return; + } } =20 static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.229; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695718578154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- meson.build | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/meson.build b/meson.build index c5710a6a47..6759dbda15 100644 --- a/meson.build +++ b/meson.build @@ -325,7 +325,8 @@ accelerator_targets +=3D { 'CONFIG_XEN': xen_targets } =20 if cpu =3D=3D 'aarch64' accelerator_targets +=3D { - 'CONFIG_HVF': ['aarch64-softmmu'] + 'CONFIG_HVF': ['aarch64-softmmu'], + 'CONFIG_WHPX': ['aarch64-softmmu'] } elif cpu =3D=3D 'x86_64' accelerator_targets +=3D { @@ -891,13 +892,18 @@ if get_option('mshv').allowed() and host_os =3D=3D 'l= inux' endif =20 if get_option('whpx').allowed() and host_os =3D=3D 'windows' - if get_option('whpx').enabled() and host_machine.cpu() !=3D 'x86_64' - error('WHPX requires 64-bit host') - elif cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ - cc.has_header('winhvemulation.h', required: get_option('whpx')) - accelerators +=3D 'CONFIG_WHPX' + if cpu =3D=3D 'i386' + if get_option('whpx').enabled() + error('WHPX requires 64-bit host') + endif + # Leave CONFIG_WHPX disabled + else + if cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ + cc.has_header('winhvemulation.h', required: get_option('whpx')) + accelerators +=3D 'CONFIG_WHPX' + endif endif -endif + endif =20 hvf =3D not_found if get_option('hvf').allowed() --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.228; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695720449154100 Content-Type: text/plain; charset="utf-8" And add arm64 files. From Pedro Barbuda (on Teams): > we meant to have that switched a while back. you can add me as the mainta= iner. Pedro Barbuda (pbarbuda@microsoft.com) Signed-off-by: Mohamed Mediouni --- MAINTAINERS | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c6b7f45459..0e7288116f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -546,11 +546,14 @@ F: accel/stubs/hvf-stub.c F: include/system/hvf.h F: include/system/hvf_int.h =20 -WHPX CPUs -M: Sunil Muthuswamy +WHPX +M: Pedro Barbuda +M: Mohamed Mediouni S: Supported F: accel/whpx/ F: target/i386/whpx/ +F: target/arm/whpx_arm.h +F: target/arm/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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Tue, 28 Oct 2025 23:49:03 +0000 (UTC) Received: from localhost.localdomain (unknown [17.57.156.36]) by p00-icloudmta-asmtp-us-central-1k-20-percent-0 (Postfix) with ESMTPSA id 79B7418034E9; Tue, 28 Oct 2025 23:49:01 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=jo9W/NpYfEdIC6CdCIx10Eqt7ku8SV4hAzngP6kYZbk=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=XIncgXhBk50Vcordu5gvwevqrJ8GSMFUSS3RnksGGjVyuj3ZLiPqfnm/RajHSbIvRUw8kiN6HycyohwsklEoGVYGGRjW4k+/mjMIfoF5YmXX9sA5Got+gQNpY9HZVyKNc5ZPgr5xyo/5UUGhRavltP2PX6DD306gm5UW+8anfSCEbe2JskKeByX1oHdPi5GK/JzI1zF8s38GHEOW5sgSqoWudqKkbYJHMK+Xk/Qi0QFCQBWBIm38MOGtHUe75l9OSYnKd9cLSzmd0aK94trJf7ImFq2Aqkqv8tzPuFMHSuXqZTq3568d3Yjn9kxXUVdYe/8IEJ6A38NqW2owuC7jIw== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: mohamed@unpredictable.fr, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Phil Dennis-Jordan , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Richard Henderson , Pedro Barbuda , Pierrick Bouvier Subject: [PATCH v9 26/27] whpx: apic: use non-deprecated APIs to control interrupt controller state Date: Wed, 29 Oct 2025 00:47:56 +0100 Message-ID: <20251028234757.39609-27-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251028234757.39609-1-mohamed@unpredictable.fr> References: <20251028234757.39609-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 8BQWhcjgj0pFxB1AX12Sp58gS_Qqy9dP X-Proofpoint-GUID: 8BQWhcjgj0pFxB1AX12Sp58gS_Qqy9dP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDIwMiBTYWx0ZWRfX2MvCCfOYXxUA LuAplZwli74JgUiJpmGEmSqWc7uwrfZwBCMR8Xc3DesPasiSYgI39252XlNNspuBQxU7pbym9ck jDWwO3432KNK1qwVdSI8zO56rsRWqJ8gUBycYSSjzhZ3lHcBW2CPpTZUaYT4VeuaQLt+hP726l0 afN1mFHj8TyJNbs+VPIJd/US0w50hGbwFl4fdTwSk/aCPlsjVzcHgb3aaBft183ujsml4AMyT1K BOTrJ1vSxzPvXpHxIwt2ximSj163BYPaaOMmwqTmdIt3mDQ+1bf4R1Z0SRc2jKEPIkLmR3Qmo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_09,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 mlxscore=0 clxscore=1030 malwarescore=0 bulkscore=0 mlxlogscore=752 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510280202 X-JNJ: AAAAAAABql2qxcO0yN7mA0ewvSlf95mNqQPItJJjeOnD/tTGo/FSyPD+ENl4hYUYVr/fF+SwbDwDpnTfE/i0hF+3w/EKsUY6oBwsd6HbtOaU84fVeZiHLmdmp0rFvL4yys6ZGzRg/5gGKDJPi8nOCJv9qDGciYF4YtTKKkp8nSnIYgnCqIAs6APJs9hcRE+Y7Q0G8d6RqVYiK3C7ADJYalKYMwBjXHDLTHMjNqIGCiYtCK94bDEFrM+rzIWSvo9lysWABbeqkbJDlmfD6NWzD/KgLx4Ylgm/VCezE4EmCW1PZ7IbRy+QdWspPe/SbVV8H3HHEVzvQBjwIuhun3bOnliogzJt4k1l6dCJfg5dtPltza7btfFXGM25ByDoOSJVfA1VHWnTHNzEN+bnZQU3G2expGUkOMpc/a0xKwsZ+0KGAsoIpFJIgdGTQuVcCPWsYU70S0f4rKUX5s0sz4mEmmf49Zkx0+2Yc4WwvCnNM79F53h9wFYqYGJML+ogiFgbCSYj+ZZ0z2frgGcJx4K5Nthe9uVXiwqLRCkMsnXXCbYIimr4x8AEFn9ymXT/kal5qX676Sq8NfEJNdf9E4SWq4EaJ9ut9Ly0h26gtEIn7iabNvtvUWfzh6lL92fGU9SDlkxCT4fP9cGAAKb/fquohAkrqH7xR3G/J1DinKDsVzAgRGJCij4mUMDZPzqB/I8G+i3k/PmhV7V5Byj2EvlUCX1h4wn7qRsACCVzaLpHrfhTkFXX6elkOEpC/liJB98esqMqlwnvyVG4eU7ZDoZGlruyUeKXfqPIcjs= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.90.209; envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1761695580472158500 Content-Type: text/plain; charset="utf-8" WHvGetVirtualProcessorInterruptControllerState2 and WHvSetVirtualProcessorInterruptControllerState2 are deprecated since Windows 10 version 2004. Use the non-deprecated WHvGetVirtualProcessorState and WHvSetVirtualProcessorState when available. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- include/system/whpx-internal.h | 9 +++++++ target/i386/whpx/whpx-apic.c | 46 +++++++++++++++++++++++++--------- 2 files changed, 43 insertions(+), 12 deletions(-) diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 81c0c1819f..90b4077b76 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -86,6 +86,15 @@ void whpx_apic_get(APICCommonState *s); X(HRESULT, WHvSetVirtualProcessorInterruptControllerState2, \ (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, PVOID State, \ UINT32 StateSize)) \ + X(HRESULT, WHvGetVirtualProcessorState, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, \ + WHV_VIRTUAL_PROCESSOR_STATE_TYPE StateType, PVOID Buffer, \ + UINT32 BufferSizeInBytes, UINT32 *BytesWritten)) \ + X(HRESULT, WHvSetVirtualProcessorState, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, \ + WHV_VIRTUAL_PROCESSOR_STATE_TYPE StateType, PVOID Buffer, \ + UINT32 BufferSizeInBytes)) \ + =20 #define LIST_WINHVEMULATION_FUNCTIONS(X) \ X(HRESULT, WHvEmulatorCreateEmulator, (const WHV_EMULATOR_CALLBACKS* Cal= lbacks, WHV_EMULATOR_HANDLE* Emulator)) \ diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index b934fdcbe1..fa45a64b21 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -137,11 +137,21 @@ static void whpx_apic_put(CPUState *cs, run_on_cpu_da= ta data) whpx_put_apic_base(CPU(s->cpu), s->apicbase); whpx_put_apic_state(s, &kapic); =20 - hr =3D whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2( - whpx_global.partition, - cs->cpu_index, - &kapic, - sizeof(kapic)); + if (whp_dispatch.WHvSetVirtualProcessorState) { + hr =3D whp_dispatch.WHvSetVirtualProcessorState( + whpx_global.partition, + cs->cpu_index, + WHvVirtualProcessorStateTypeInterruptControllerState2, + &kapic, + sizeof(kapic)); + } else { + hr =3D whp_dispatch.WHvSetVirtualProcessorInterruptControllerState= 2( + whpx_global.partition, + cs->cpu_index, + &kapic, + sizeof(kapic)); + } + if (FAILED(hr)) { fprintf(stderr, "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\= n", @@ -155,16 +165,28 @@ void whpx_apic_get(APICCommonState *s) { CPUState *cpu =3D CPU(s->cpu); struct whpx_lapic_state kapic; + HRESULT hr; + + if (whp_dispatch.WHvGetVirtualProcessorState) { + hr =3D whp_dispatch.WHvGetVirtualProcessorState( + whpx_global.partition, + cpu->cpu_index, + WHvVirtualProcessorStateTypeInterruptControllerState2, + &kapic, + sizeof(kapic), + NULL); + } else { + hr =3D whp_dispatch.WHvGetVirtualProcessorInterruptControllerState= 2( + whpx_global.partition, + cpu->cpu_index, + &kapic, + sizeof(kapic), + NULL); + } =20 - HRESULT hr =3D whp_dispatch.WHvGetVirtualProcessorInterruptControllerS= tate2( - whpx_global.partition, - cpu->cpu_index, - &kapic, - sizeof(kapic), - NULL); if (FAILED(hr)) { fprintf(stderr, - "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\= n", + "WHvGetVirtualProcessorInterruptControllerState failed: %08lx\= n", hr); =20 abort(); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 18:21:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1761695849; cv=none; d=zohomail.com; s=zohoarc; b=U0onTm2i1JV7GaSiarG7zLRKIedffwy3wYvMaFLaYWPbL0d1iqXiflxiPELZUg4utDc6Nk+gh8T9qNw0P7XfN1a/mOiLm07dfslkCyuX05JnDcEN4A7fNdZyy1/Hb04hTOenz/V3ODl5ND6ojpkHnydisihYOACAWWC7ENIbz/s= ARC-Message-Signature: i=1; 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s=sig1; bh=NOUCweN0BwDWHptjKrVueVuLmTbPgqxKBFU13NRtxRY=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=MDDPaQX17aV3HRYTDTH8E4FoXvcVl4EcTw2Cc1pB68OyArEfFei3mQqXj9rtmNto1DI62+MQce9ovSRaAdJnUJcmr29DcBXOEUF4YvaJyFxj1bbG6OAOEL+jnNu3BRNtmYU8fTAiQV5JqcxGc/KPykTtYKC88RTpN2mWto17d+U/sCWskpeXJ9F/t85uDgSW56iriHo6SrqYAawFa/Ns1EA33+fpmJsDWqPwoT9S2UY73Q4g7UBqHJ4AZXQkKLuMiJ3Il+mz1px6rGfWlXoDMaDC29q1Dbrio+nJgGGjiKl6YGhvKGLog9l2vv7FKmdRhaCfgRmPDa1/9hi4+ol/sw== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: mohamed@unpredictable.fr, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Phil Dennis-Jordan , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Richard Henderson , Pedro Barbuda Subject: [PATCH v9 27/27] whpx: arm64: check for physical address width after WHPX availability Date: Wed, 29 Oct 2025 00:47:57 +0100 Message-ID: <20251028234757.39609-28-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251028234757.39609-1-mohamed@unpredictable.fr> References: <20251028234757.39609-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: q180pRIWLh2vrRiXFFtitRwYoTnDSBkl X-Proofpoint-GUID: q180pRIWLh2vrRiXFFtitRwYoTnDSBkl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDIwMiBTYWx0ZWRfX2KM4z4Wk+ote n7S516Q8zlau66WwP0dBwmLJV/p+1NXhFBcrQxOjMOIeXhUVEhOSSTF24GBg7Y591lAq6Xim84U LKtA+kM9FrbXkQtUWQdDOd9MHD679w0AoSZEw54SBgiFTh5R9M6OPlLyY0rgJbk4yu3YkERXNkX IFZwmgbefN/KyTC/WiCBn06KuWnqoFXUkT4rDDHmai/moafdIxTy6L5BMSIuaFNvGKWQUlOxtKz hit0/bsBm9rc3Swf14iD6zF0P2CWP6wS79YW6MdyjcFfl+8SSdAZsPYsqOQWaRRa25uWH7IBo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_09,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 adultscore=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxscore=0 mlxlogscore=917 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510280202 X-JNJ: AAAAAAABkTyMLHnih2WDsD9g2Xmak0m5J9ZdM6LTu4SvojoZSkg9miz2DpQ3ahICiQ2XIehw8xaJIG2pCwbFHXZcVNyt7BmIMhAcdkNXaWMAVH0lKask/X4sZY26zcrvk+bYcE1g1NUzncCmq6hJYi21LiYncuYlvAsDEuDoH+Ipf5/qT6A6z17VhcHVFxssUi2sJU+RQZMx3D9EU4at3KHIsHSPyAoSY5fDE2GxWnaCDmhRovsXulpGjMf35WALgrZ9JKxWPkZqlt67ztvhnlXHkGf/XGd7lOl47Cpsm+OyGLIP1SpXQIAgFjjuhD6dgZw1egC2pMSZxMyZDMoocYUxvWxL06A7vdg5jmTpdgXTyqZAM8u+vB2S2wVopcQelQ14omGfiMg9fC2F4Z14rkcMVsX9R9sK3n7XEBVpuAAz+uXP7WB2FCQaNAg0WGAONJQXcuKY2b51n9cykj6l7eNwnVz9314KF0eNABUKvXTEDmBYNHTqh5rwS4yu2AGAqp8CcZv2fuBL/r4ioi+NRTJNhuNKDG/7aibzC9S5cnP3nEE4J+OXZ+mtPnSDMMqfzEjWrbdNOTBzUlDPof/gkJJEsGcyOjatcC/gOn6hmWedmnkUDn4hBDr6w4jtLF4REPKbccKuvUiLT63IiUSUZ+6nC+S15BUkKyULPXcmTbJyAgXm38DKfn0RaS5Xtwvttou68VzFRiwaXUUJxSfXNgH+H3IxLD4K9qKFXVJG5n5GOeHS3mM6F/eOn4ptF+YE Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In the case where WHPX isn't supported on the platform, makes the intended error appear instead of failing at getting the IPA width. Signed-off-by: Mohamed Mediouni --- target/arm/whpx/whpx-all.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 4d58e5e939..ce1794952c 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -678,7 +678,7 @@ uint32_t whpx_arm_get_ipa_bit_size(void) WHvCapabilityCodePhysicalAddressWidth, &whpx_cap, sizeof(whpx_cap), &whpx_cap_size); if (FAILED(hr)) { - error_report("WHPX: failed to get supported" + error_report("WHPX: failed to get supported " "physical address width, hr=3D%08lx", hr); } =20 @@ -909,14 +909,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - if (mc->get_physical_address_range) { - pa_range =3D mc->get_physical_address_range(ms, - whpx_arm_get_ipa_bit_size(), whpx_arm_get_ipa_bit_size()); - if (pa_range < 0) { - return -EINVAL; - } - } - whpx->mem_quota =3D ms->ram_size; =20 hr =3D whp_dispatch.WHvGetCapability( @@ -943,6 +935,14 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + whpx_arm_get_ipa_bit_size(), whpx_arm_get_ipa_bit_size()); + if (pa_range < 0) { + return -EINVAL; + } + } + hr =3D whp_dispatch.WHvCreatePartition(&whpx->partition); if (FAILED(hr)) { error_report("WHPX: Failed to create partition, hr=3D%08lx", hr); --=20 2.50.1 (Apple Git-155)