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Tue, 28 Oct 2025 00:57:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org Subject: [PULL 22/23] hw/riscv: Use generic hwaddr for firmware addresses Date: Tue, 28 Oct 2025 08:48:58 +0100 Message-ID: <20251028074901.22062-23-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251028074901.22062-1-philmd@linaro.org> References: <20251028074901.22062-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761638247358154100 From: Anton Johansson Signed-off-by: Anton Johansson Message-ID: <20251027-feature-single-binary-hw-v1-v2-1-44478d589ae9@rev.ng> Reviewed-by: Philippe Mathieu-Daud=C3=A9 [PMD: Do not update riscv_load_kernel()] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/boot.h | 18 +++++++++--------- hw/riscv/boot.c | 20 ++++++++++---------- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 2 +- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7d59b2e6c63..51b0e13bd3e 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,18 +43,18 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); =20 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr); -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firm= ware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr); +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); char *riscv_find_firmware(const char *firmware_filename, const char *default_machine_firmware); -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, target_ulong kernel_start_addr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index f38078c8c22..9510fca939b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartA= rrayState *harts) info->is_32bit =3D riscv_is_32bit(harts); } =20 -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr) { +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr) { if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { @@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filena= me, return filename; } =20 -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firm= ware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename; - target_ulong firmware_end_addr =3D *firmware_load_addr; + hwaddr firmware_end_addr =3D *firmware_load_addr; =20 firmware_filename =3D riscv_find_firmware(machine->firmware, default_machine_firmware); @@ -154,9 +154,9 @@ target_ulong riscv_find_and_load_firmware(MachineState = *machine, return firmware_end_addr; } =20 -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { uint64_t firmware_entry, firmware_end; ssize_t firmware_size; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4c939d8e96c..a17f62cd082 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -521,7 +521,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) uint64_t mem_low_size, mem_high_size; hwaddr firmware_load_addr; const char *firmware_name; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; uint64_t fdt_load_addr; DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3e1ed209ca9..a7492aa27a4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -515,7 +515,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); hwaddr start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; const char *firmware_name; uint32_t start_addr_hi32 =3D 0x00000000; uint32_t fdt_load_addr_hi32 =3D 0x00000000; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 641aae8c019..b0bab3fe008 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -197,9 +197,9 @@ static void spike_board_init(MachineState *machine) SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - target_ulong firmware_end_addr =3D memmap[SPIKE_DRAM].base; + hwaddr firmware_end_addr =3D memmap[SPIKE_DRAM].base; hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base; - target_ulong kernel_start_addr; + hwaddr kernel_start_addr; char *firmware_name; uint64_t fdt_load_addr; uint64_t kernel_entry; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 47e573f85ab..17909206c7e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1434,7 +1434,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); uint64_t fdt_load_addr; uint64_t kernel_entry =3D 0; --=20 2.51.0