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In update_fr0_op() we incorrectly zero out the flag bits and the C bit, so any fp operation would clear previously set flag bits. We also stopped setting the flag bits when the fp operation raises an exception and the trap is not enabled. Adjust the code so that we set the Flag bits for every exception that happened and where the trap is not enabled. (This is the correct behaviour for the case where an instruction triggers two exceptions, one of which traps and one of which does not; that can only happen for inexact + underflow or inexact + overflow.) Cc: qemu-stable@nongnu.org Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 Signed-off-by: Peter Maydell Reviewed-by: Helge Deller Tested-by: Helge Deller Message-ID: <20251017085350.895681-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/fpu_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 45353202fae..2d272730f60 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) { uint32_t soft_exp =3D get_float_exception_flags(&env->fp_status); uint32_t hard_exp =3D 0; - uint32_t shadow =3D env->fr0_shadow & 0x3ffffff; + uint32_t shadow =3D env->fr0_shadow; + uint32_t to_flag =3D 0; uint32_t fr1 =3D 0; =20 if (likely(soft_exp =3D=3D 0)) { @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t= ra) fr1 |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIF= T); } } + /* Set the Flag bits for every exception that was not enabled */ + to_flag =3D hard_exp & ~shadow; + shadow |=3D to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); + env->fr0_shadow =3D shadow; env->fr[0] =3D (uint64_t)shadow << 32 | fr1; =20 --=20 2.51.0