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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- target/arm/hvf/hvf.c | 14 ++++++++------ target/arm/hvf/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index c882f4c89cf..26bafee259e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1149,7 +1149,8 @@ static uint32_t hvf_reg2cp_reg(uint32_t reg) (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); } =20 -static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) +static bool hvf_sysreg_read_cp(CPUState *cpu, const char *cpname, + uint32_t reg, uint64_t *val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; @@ -1172,7 +1173,7 @@ static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_= t reg, uint64_t *val) } else { *val =3D raw_read(env, ri); } - trace_hvf_vgic_read(ri->name, *val); + trace_hvf_emu_reginfo_read(cpname, ri->name, *val); return true; } =20 @@ -1261,7 +1262,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) case SYSREG_ICC_SRE_EL1: case SYSREG_ICC_CTLR_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ - if (hvf_sysreg_read_cp(cpu, reg, val)) { + if (hvf_sysreg_read_cp(cpu, "GICv3", reg, val)) { return 0; } break; @@ -1432,7 +1433,8 @@ static void pmswinc_write(CPUARMState *env, uint64_t = value) } } =20 -static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) +static bool hvf_sysreg_write_cp(CPUState *cpu, const char *cpname, + uint32_t reg, uint64_t val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; @@ -1455,7 +1457,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32= _t reg, uint64_t val) raw_write(env, ri, val); } =20 - trace_hvf_vgic_write(ri->name, val); + trace_hvf_emu_reginfo_write(cpname, ri->name, val); return true; } =20 @@ -1581,7 +1583,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: /* Call the TCG sysreg handler. This is only safe for GICv3 regs. = */ - if (hvf_sysreg_write_cp(cpu, reg, val)) { + if (hvf_sysreg_write_cp(cpu, "GICv3", reg, val)) { return 0; } break; diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events index 538af6e0707..29387780e3f 100644 --- a/target/arm/hvf/trace-events +++ b/target/arm/hvf/trace-events @@ -9,7 +9,7 @@ hvf_unknown_hvc(uint64_t pc, uint64_t x0) "pc=3D0x%"PRIx64"= unknown HVC! 0x%016"PR hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [= ec=3D0x%x pc=3D0x%"PRIx64"]" hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpuid=3D0x%x" -hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=3D0x= %016"PRIx64"]" -hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=3D0x= %016"PRIx64"]" +hvf_emu_reginfo_write(const char *cpname, const char *regname, uint64_t va= l) "[%s] write to %s [val=3D0x%016"PRIx64"]" +hvf_emu_reginfo_read(const char *cpname, const char *regname, uint64_t val= ) "[%s] read from %s [val=3D0x%016"PRIx64"]" hvf_illegal_guest_state(void) "HV_ILLEGAL_GUEST_STATE" hvf_kick_vcpu_thread(unsigned cpuidx, bool stop) "cpu:%u stop:%u" --=20 2.51.0