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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/7] hw/pci/pci_host: Add 'config-reg-check-high-bit' property Date: Mon, 27 Oct 2025 17:52:57 +0100 Message-ID: <20251027165304.98296-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584093751154100 In order to have more PCI host bridges to re-use the generic pci_host_data_le_ops MemoryRegionOps, add the 'config-reg-check-high-bit' property (%true by default). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci/pci_host.h | 1 + hw/pci/pci_host.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 954dd446fa4..c04a567ec57 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -43,6 +43,7 @@ struct PCIHostState { MemoryRegion data_mem; MemoryRegion mmcfg; uint32_t config_reg; + bool config_reg_check_high_bit; bool mig_enabled; PCIBus *bus; bool bypass_iommu; diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index b5c624e12e8..d6db365e327 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -184,8 +184,10 @@ static void pci_host_data_write(void *opaque, hwaddr a= ddr, { PCIHostState *s =3D opaque; =20 - if (s->config_reg & (1u << 31)) - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { + return; + } + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); } =20 static uint64_t pci_host_data_read(void *opaque, @@ -193,7 +195,7 @@ static uint64_t pci_host_data_read(void *opaque, { PCIHostState *s =3D opaque; =20 - if (!(s->config_reg & (1U << 31))) { + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { return 0xffffffff; } return pci_data_read(s->bus, s->config_reg | (addr & 3), len); @@ -235,6 +237,8 @@ const VMStateDescription vmstate_pcihost =3D { }; =20 static const Property pci_host_properties_common[] =3D { + DEFINE_PROP_BOOL("config-reg-check-high-bit", PCIHostState, + config_reg_check_high_bit, true), DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, fa= lse), --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761584107; cv=none; d=zohomail.com; s=zohoarc; b=J2hA6GYnaO4YuQoVgQntENsKxhqc5LKOposhnA6LTTiv8+sqVEqgd8ut5iMnl7RYaHRnZVUxh9amzVU3q2m2fEd9mEpjaffGTPddp8c5CHZZnubO/L1mV96NrcT3LU5Yg/o7kZx3law7PJx9jRds59HT4DjQzoCwD+An4FZxrBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761584107; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=w5AYcZWKjl+z3UUAUBIKeSJtay1TyUPTtzgR0XhDmJM=; b=ebfeGS8vBYTxuVqo0PW3vtfBrwXZyFfVTmt75p2F3oASHN2tbUQ7dpU/PsUZSAXOm5DhVJKs8C/VJNf0nxfriZQLs+54KGqGtPxwiqzCS2WYJVkxIfzSh9r+jBHQjHOihHu3gIC7sJiZXUQ1Eg0JUZT3WXqT4K6ULe+kt4GHRHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761584106987293.28488861826884; Mon, 27 Oct 2025 09:55:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDQUF-0001Gl-Jk; Mon, 27 Oct 2025 12:54:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDQUC-0001G1-6e for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:54:24 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vDQU5-000122-KB for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:54:23 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4770c2cd96fso14417835e9.3 for ; Mon, 27 Oct 2025 09:54:13 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/7] hw/pci-host/astro: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 17:52:58 +0100 Message-ID: <20251027165304.98296-3-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584107930154101 Avoid duplicating code, clear the "config-reg-check-high-bit" property in .instance_init() in order to re-use the generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/astro.c | 35 ++++++++--------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 0bd66ab3de3..72e625c2508 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -230,32 +230,6 @@ static const MemoryRegionOps elroy_chip_ops =3D { }; =20 =20 -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ - -static uint64_t elroy_config_data_read(void *opaque, hwaddr addr, unsigned= len) -{ - uint64_t val; - - PCIHostState *s =3D opaque; - val =3D pci_data_read(s->bus, s->config_reg | (addr & 3), len); - trace_elroy_pci_config_data_read(s->config_reg | (addr & 3), len, val); - return val; -} - -static void elroy_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s =3D opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); - trace_elroy_pci_config_data_write(s->config_reg | (addr & 3), len, val= ); -} - -static const MemoryRegionOps elroy_config_data_ops =3D { - .read =3D elroy_config_data_read, - .write =3D elroy_config_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static uint64_t elroy_config_addr_read(void *opaque, hwaddr addr, unsigned= len) { ElroyState *s =3D opaque; @@ -424,6 +398,12 @@ static void elroy_reset(DeviceState *dev) } } =20 +static void elroy_pcihost_instance_init(Object *obj) +{ + object_property_set_bool(obj, "config-reg-check-high-bit", false, + &error_fatal); +} + static void elroy_pcihost_realize(DeviceState *dev, Error **errp) { ElroyState *s =3D ELROY_PCI_HOST_BRIDGE(dev); @@ -440,7 +420,7 @@ static void elroy_pcihost_realize(DeviceState *dev, Err= or **errp) &elroy_config_addr_ops, dev, "pci-conf-idx", 8); memory_region_init_io(&phb->data_mem, obj, - &elroy_config_data_ops, dev, + &pci_host_data_le_ops, phb, "pci-conf-data", 8); memory_region_add_subregion(&s->this_mem, 0x40, &phb->conf_mem); @@ -497,6 +477,7 @@ static const TypeInfo elroy_pcihost_info =3D { .name =3D TYPE_ELROY_PCI_HOST_BRIDGE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(ElroyState), + .instance_init =3D elroy_pcihost_instance_init, .class_init =3D elroy_pcihost_class_init, }; =20 diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index a6fd88c2c46..792ab25729b 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -76,7 +76,5 @@ astro_chip_read(uint64_t addr, int size, uint64_t val) "a= ddr 0x%"PRIx64" size %d astro_chip_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" = size %d val 0x%"PRIx64 elroy_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %= d val 0x%"PRIx64 elroy_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size = %d val 0x%"PRIx64 -elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x= %"PRIx64" size %d val 0x%"PRIx64 -elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0= x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select= 0x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select = 0x%"PRIx64" size %d val 0x%"PRIx64 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/7] hw/pci-host/dino: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 17:52:59 +0100 Message-ID: <20251027165304.98296-4-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584132234154100 Avoid duplicating code, clear the "config-reg-check-high-bit" property in .instance_init() in order to re-use the generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/dino.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c index 924053499c1..31ffe8fa60d 100644 --- a/hw/pci-host/dino.c +++ b/hw/pci-host/dino.c @@ -302,27 +302,6 @@ static const VMStateDescription vmstate_dino =3D { } }; =20 -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ - -static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned = len) -{ - PCIHostState *s =3D opaque; - return pci_data_read(s->bus, s->config_reg | (addr & 3), len); -} - -static void dino_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s =3D opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); -} - -static const MemoryRegionOps dino_config_data_ops =3D { - .read =3D dino_config_data_read, - .write =3D dino_config_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned = len) { DinoState *s =3D opaque; @@ -410,6 +389,12 @@ static void dino_pcihost_reset(DeviceState *dev) s->toc_addr =3D 0xFFFA0030; /* IO_COMMAND of CPU */ } =20 +static void dino_pcihost_instance_init(Object *obj) +{ + object_property_set_bool(obj, "config-reg-check-high-bit", false, + &error_fatal); +} + static void dino_pcihost_realize(DeviceState *dev, Error **errp) { DinoState *s =3D DINO_PCI_HOST_BRIDGE(dev); @@ -424,7 +409,7 @@ static void dino_pcihost_realize(DeviceState *dev, Erro= r **errp) &dino_config_addr_ops, DEVICE(s), "pci-conf-idx", 4); memory_region_init_io(&phb->data_mem, OBJECT(phb), - &dino_config_data_ops, DEVICE(s), + &pci_host_data_le_ops, phb, "pci-conf-data", 4); memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, &phb->conf_mem); @@ -505,6 +490,7 @@ static const TypeInfo dino_pcihost_info =3D { .name =3D TYPE_DINO_PCI_HOST_BRIDGE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(DinoState), + .instance_init =3D dino_pcihost_instance_init, .class_init =3D dino_pcihost_class_init, }; =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761584178; cv=none; d=zohomail.com; s=zohoarc; b=fQQ4A9RrJk5qZlCwUGYO8LeGa3bbAvvlCmgj4KvTk1ax/6Gz+6HXAha53gIh+MTxMKG/dks/XsXfOAdirgAKZSl1S/IFbvRXMzevaMj/hGHGbf4r6HsjckCE7ZsjUh8DN4+u3hQusSNyTst8+eKUCNBBrNsmFPBQQ14bFdqWNLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761584178; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mR9y4rf3YIHAZI+0OjgGmLH7QJrVR3WgUfA1D6HdoHU=; b=FMmbIQ3FWf4Haf+9I8rLU8z5OWar3rgxNzI/taqsEyKxDN0qGO5YLpkpoFpGMTnBlf0M/pcEagIcCHLKbHGvxWlQXft7TCGPIQzepYdt2rVnmu0tRLfKkglu/BojgxwBNdxrcf0dH3MGXpWHSrulMmNTH7izfxGdkqQvGmlTj/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761584178321626.2187345562902; Mon, 27 Oct 2025 09:56:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDQVc-0002ts-Nt; Mon, 27 Oct 2025 12:55:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDQVH-0002aU-Ps for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:55:32 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vDQV5-0001Ih-GP for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:55:31 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-42421b1514fso3486768f8f.2 for ; Mon, 27 Oct 2025 09:55:17 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/7] hw/pci-host/sabre: Remove pointless OBJECT() cast Date: Mon, 27 Oct 2025 17:53:00 +0100 Message-ID: <20251027165304.98296-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584182733158501 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/sabre.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f95e5db583a..f63d832efc0 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -429,18 +429,18 @@ static void sabre_init(Object *obj) 0); =20 /* sabre_config */ - memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, = s, + memory_region_init_io(&s->sabre_config, obj, &sabre_config_ops, s, "sabre-config", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->sabre_config); =20 - memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, + memory_region_init_io(&s->pci_config, obj, &pci_config_ops, s, "sabre-pci-config", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); =20 /* pci_ioport */ - memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", + memory_region_init(&s->pci_ioport, obj, "sabre-pci-ioport", 0x1000000); =20 /* at region 2 */ --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761584208; cv=none; d=zohomail.com; s=zohoarc; b=aKcduWnWnEaiCHinC1S+mqMNbhjHzQscyHWudWuMSpzcNrJFOJktR/sz5Nj82CCDZp7z/n/b0IkW4mIXNM2z3Zqk52dZw33HoPG8cPes6t8FAWsr7SPXAgc2tMGlNtOjqHMQulalNXGwO3Zh0todohKjXbHoPDcWwmL/+MJOPOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761584208; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rJWsP8lU8vlleE35z63JKOE98MNb43nWOSZHGlrXrmY=; b=ARCZCkRMPgrNkh61ufI67gnEgT1ISDciOJTTQCy+b9pHY+7PmRFSOVh4TP2CK/jMzIzJ1bVe9aNYJdBpPlD1fcm8mHdF4bhD1LuiEn7Vb4czfvTzKI2cHk0LNHdpBmRNt5ynLQk8VqEGMTdVGiFL+2QB27o81m2wlRjlpjY/b+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176158420865771.12245808943749; Mon, 27 Oct 2025 09:56:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDQWL-0003dT-MG; Mon, 27 Oct 2025 12:56:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDQVz-0003Qd-F7 for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:56:16 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vDQVd-0001MM-Oa for qemu-devel@nongnu.org; Mon, 27 Oct 2025 12:56:11 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-4298b49f103so1623189f8f.2 for ; Mon, 27 Oct 2025 09:55:50 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/7] hw/pci-host/sabre: Include 'host' in host bridge method names Date: Mon, 27 Oct 2025 17:53:01 +0100 Message-ID: <20251027165304.98296-6-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584211240154100 Rename various methods to help distinguish between sabre_host* (for host bridge block) and sabre_pci* (for the PCI function). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/sabre.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f63d832efc0..669191b6c7e 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -116,8 +116,8 @@ static const PCIIOMMUOps sabre_iommu_ops =3D { .get_address_space =3D sabre_pci_dma_iommu, }; =20 -static void sabre_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void sabre_host_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { SabreState *s =3D opaque; =20 @@ -194,8 +194,8 @@ static void sabre_config_write(void *opaque, hwaddr add= r, } } =20 -static uint64_t sabre_config_read(void *opaque, - hwaddr addr, unsigned size) +static uint64_t sabre_host_config_read(void *opaque, + hwaddr addr, unsigned size) { SabreState *s =3D opaque; uint32_t val =3D 0; @@ -240,9 +240,9 @@ static uint64_t sabre_config_read(void *opaque, return val; } =20 -static const MemoryRegionOps sabre_config_ops =3D { - .read =3D sabre_config_read, - .write =3D sabre_config_write, +static const MemoryRegionOps sabre_host_config_ops =3D { + .read =3D sabre_host_config_read, + .write =3D sabre_host_config_write, .endianness =3D DEVICE_BIG_ENDIAN, }; =20 @@ -329,7 +329,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num= , int level) } } =20 -static void sabre_reset(DeviceState *d) +static void sabre_host_reset(DeviceState *d) { SabreState *s =3D SABRE(d); PCIDevice *pci_dev; @@ -367,7 +367,7 @@ static const MemoryRegionOps pci_config_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static void sabre_realize(DeviceState *dev, Error **errp) +static void sabre_host_realize(DeviceState *dev, Error **errp) { SabreState *s =3D SABRE(dev); PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); @@ -402,7 +402,7 @@ static void sabre_realize(DeviceState *dev, Error **err= p) pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); } =20 -static void sabre_init(Object *obj) +static void sabre_host_instance_init(Object *obj) { SabreState *s =3D SABRE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); @@ -429,7 +429,7 @@ static void sabre_init(Object *obj) 0); =20 /* sabre_config */ - memory_region_init_io(&s->sabre_config, obj, &sabre_config_ops, s, + memory_region_init_io(&s->sabre_config, obj, &sabre_host_config_ops, s, "sabre-config", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->sabre_config); @@ -483,7 +483,7 @@ static const TypeInfo sabre_pci_info =3D { }, }; =20 -static char *sabre_ofw_unit_address(const SysBusDevice *dev) +static char *sabre_host_ofw_unit_address(const SysBusDevice *dev) { SabreState *s =3D SABRE(dev); =20 @@ -492,34 +492,34 @@ static char *sabre_ofw_unit_address(const SysBusDevic= e *dev) (uint32_t)(s->special_base & 0xffffffff)); } =20 -static const Property sabre_properties[] =3D { +static const Property sabre_host_properties[] =3D { DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), }; =20 -static void sabre_class_init(ObjectClass *klass, const void *data) +static void sabre_host_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); SysBusDeviceClass *sbc =3D SYS_BUS_DEVICE_CLASS(klass); =20 - dc->realize =3D sabre_realize; - device_class_set_legacy_reset(dc, sabre_reset); - device_class_set_props(dc, sabre_properties); + dc->realize =3D sabre_host_realize; + device_class_set_legacy_reset(dc, sabre_host_reset); + device_class_set_props(dc, sabre_host_properties); dc->fw_name =3D "pci"; - sbc->explicit_ofw_unit_address =3D sabre_ofw_unit_address; + sbc->explicit_ofw_unit_address =3D sabre_host_ofw_unit_address; } =20 -static const TypeInfo sabre_info =3D { +static const TypeInfo sabre_host_info =3D { .name =3D TYPE_SABRE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(SabreState), - .instance_init =3D sabre_init, - .class_init =3D sabre_class_init, + .instance_init =3D sabre_host_instance_init, + .class_init =3D sabre_host_class_init, }; =20 static void sabre_register_types(void) { - type_register_static(&sabre_info); + type_register_static(&sabre_host_info); type_register_static(&sabre_pci_info); } =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/7] hw/pci-host/sabre: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 17:53:02 +0100 Message-ID: <20251027165304.98296-7-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584253470158500 Avoid duplicating code, re-use the generic generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/sabre.c | 34 +++------------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 3 insertions(+), 33 deletions(-) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 669191b6c7e..eb3dbe3361f 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -246,28 +246,6 @@ static const MemoryRegionOps sabre_host_config_ops =3D= { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void sabre_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - SabreState *s =3D opaque; - PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - - trace_sabre_pci_config_write(addr, val); - pci_data_write(phb->bus, addr, val, size); -} - -static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, - unsigned size) -{ - uint32_t ret; - SabreState *s =3D opaque; - PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - - ret =3D pci_data_read(phb->bus, addr, size); - trace_sabre_pci_config_read(addr, ret); - return ret; -} - /* The sabre host has an IRQ line for each IRQ line of each slot. */ static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { @@ -361,12 +339,6 @@ static void sabre_host_reset(DeviceState *d) pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); } =20 -static const MemoryRegionOps pci_config_ops =3D { - .read =3D sabre_pci_config_read, - .write =3D sabre_pci_config_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void sabre_host_realize(DeviceState *dev, Error **errp) { SabreState *s =3D SABRE(dev); @@ -430,12 +402,12 @@ static void sabre_host_instance_init(Object *obj) =20 /* sabre_config */ memory_region_init_io(&s->sabre_config, obj, &sabre_host_config_ops, s, - "sabre-config", 0x10000); + "pci-conf-idx", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->sabre_config); =20 - memory_region_init_io(&s->pci_config, obj, &pci_config_ops, s, - "sabre-pci-config", 0x1000000); + memory_region_init_io(&s->pci_config, obj, &pci_host_data_le_ops, s, + "pci-data-idx", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); =20 diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 792ab25729b..20c3cae47a2 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -35,8 +35,6 @@ sabre_set_request(int irq_num) "request irq %d" sabre_clear_request(int irq_num) "clear request irq %d" sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"= PRIx64 sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"P= RIx64 -sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val = 0x%"PRIx64 -sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0= x%"PRIx64 sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 7/7] hw/pci-host/typhoon: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 17:53:03 +0100 Message-ID: <20251027165304.98296-8-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761584253681154100 Avoid duplicating code, re-use the generic generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/alpha/alpha_sys.h | 1 - hw/alpha/pci.c | 26 -------------------------- hw/alpha/typhoon.c | 4 ++-- 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/hw/alpha/alpha_sys.h b/hw/alpha/alpha_sys.h index a303c584383..c193f0a9b56 100644 --- a/hw/alpha/alpha_sys.h +++ b/hw/alpha/alpha_sys.h @@ -14,7 +14,6 @@ PCIBus *typhoon_init(MemoryRegion *, qemu_irq *, qemu_irq= *, AlphaCPU *[4], =20 /* alpha_pci.c. */ extern const MemoryRegionOps alpha_pci_ignore_ops; -extern const MemoryRegionOps alpha_pci_conf1_ops; extern const MemoryRegionOps alpha_pci_iack_ops; =20 #endif diff --git a/hw/alpha/pci.c b/hw/alpha/pci.c index 7c18297177b..d44cee570bf 100644 --- a/hw/alpha/pci.c +++ b/hw/alpha/pci.c @@ -38,32 +38,6 @@ const MemoryRegionOps alpha_pci_ignore_ops =3D { }, }; =20 - -/* PCI config space reads/writes, to byte-word addressable memory. */ -static uint64_t bw_conf1_read(void *opaque, hwaddr addr, - unsigned size) -{ - PCIBus *b =3D opaque; - return pci_data_read(b, addr, size); -} - -static void bw_conf1_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PCIBus *b =3D opaque; - pci_data_write(b, addr, val, size); -} - -const MemoryRegionOps alpha_pci_conf1_ops =3D { - .read =3D bw_conf1_read, - .write =3D bw_conf1_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 4, - }, -}; - /* PCI/EISA Interrupt Acknowledge Cycle. */ =20 static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 4c56f981d71..f5a9d6e6ed4 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -911,8 +911,8 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa= _irq, &s->pchip.reg_iack); =20 /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */ - memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_= ops, - b, "pci0-conf", 16 * MiB); + memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &pci_host_data_le= _ops, + phb, "pci0-data-idx", 16 * MiB); memory_region_add_subregion(addr_space, 0x801fe000000ULL, &s->pchip.reg_conf); =20 --=20 2.51.0