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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/4] hw/pci/pci_host: Add 'config-reg-check-high-bit' property Date: Mon, 27 Oct 2025 14:30:34 +0100 Message-ID: <20251027133037.70487-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761571917038154100 In order to have more PCI host bridges to re-use the generic pci_host_data_le_ops MemoryRegionOps, add the 'config-reg-check-high-bit' property (%true by default). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci/pci_host.h | 1 + hw/pci/pci_host.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 954dd446fa4..c04a567ec57 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -43,6 +43,7 @@ struct PCIHostState { MemoryRegion data_mem; MemoryRegion mmcfg; uint32_t config_reg; + bool config_reg_check_high_bit; bool mig_enabled; PCIBus *bus; bool bypass_iommu; diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index b5c624e12e8..06003188e1d 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -184,8 +184,10 @@ static void pci_host_data_write(void *opaque, hwaddr a= ddr, { PCIHostState *s =3D opaque; =20 - if (s->config_reg & (1u << 31)) - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { + return; + } + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); } =20 static uint64_t pci_host_data_read(void *opaque, @@ -193,7 +195,7 @@ static uint64_t pci_host_data_read(void *opaque, { PCIHostState *s =3D opaque; =20 - if (!(s->config_reg & (1U << 31))) { + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { return 0xffffffff; } return pci_data_read(s->bus, s->config_reg | (addr & 3), len); @@ -237,6 +239,8 @@ const VMStateDescription vmstate_pcihost =3D { static const Property pci_host_properties_common[] =3D { DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), + DEFINE_PROP_BOOL("config-reg-check-high-bit", PCIHostState, + config_reg_check_high_bit, true), DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, fa= lse), }; =20 --=20 2.51.0 From nobody Fri Nov 14 18:15:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761571938; cv=none; d=zohomail.com; s=zohoarc; b=WbIQ21m27k2q5qv6m3mC/fQG8pqDrjd1xSNqPHGXXFIU6MOKDo70PHRYLSGQ6YBQEKqB9e/K6ebTIbnyCcMkK3jbDz1zLvj7OhxuKHH3tKE4DH7GIIDDuTnhR5kZSJskxWKy978J/z3NhagJpnBE0mCV+6S56huswf2YEsklhLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761571938; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZAKUljJ3Ki5HyrVPMR5JskJBV5m6bECGQrsJLrYoqxs=; b=h7BAfsjbt1uaXYITN0Rr7p4cVKxcLLrWeQoDufGtGlGeeJwvRJsDjZADqD7Tbb4amp7Be2ap7xNOHmSEp78yQKQyFcLE26WfMoFo7gZx7/6Vu5GWPr7GGQfNuHMFmkYTwOX9MObrFtLqJOzOxjdCKwgF1VX4j8zooeuU2eTqfyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176157193893711.713611678952361; Mon, 27 Oct 2025 06:32:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDNKM-00073D-S7; Mon, 27 Oct 2025 09:32:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDNKJ-000711-Pc for qemu-devel@nongnu.org; Mon, 27 Oct 2025 09:32:00 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vDNKA-0006bb-Ba for qemu-devel@nongnu.org; Mon, 27 Oct 2025 09:31:59 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-474975af41dso32603075e9.2 for ; Mon, 27 Oct 2025 06:31:47 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/4] hw/pci-host/astro: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 14:30:35 +0100 Message-ID: <20251027133037.70487-3-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761571941287154100 Avoid duplicating code, clear the "config-reg-check-high-bit" property in .instance_init() in order to re-use the generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/astro.c | 35 ++++++++--------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 0bd66ab3de3..110070486d7 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -230,32 +230,6 @@ static const MemoryRegionOps elroy_chip_ops =3D { }; =20 =20 -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ - -static uint64_t elroy_config_data_read(void *opaque, hwaddr addr, unsigned= len) -{ - uint64_t val; - - PCIHostState *s =3D opaque; - val =3D pci_data_read(s->bus, s->config_reg | (addr & 3), len); - trace_elroy_pci_config_data_read(s->config_reg | (addr & 3), len, val); - return val; -} - -static void elroy_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s =3D opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); - trace_elroy_pci_config_data_write(s->config_reg | (addr & 3), len, val= ); -} - -static const MemoryRegionOps elroy_config_data_ops =3D { - .read =3D elroy_config_data_read, - .write =3D elroy_config_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static uint64_t elroy_config_addr_read(void *opaque, hwaddr addr, unsigned= len) { ElroyState *s =3D opaque; @@ -424,6 +398,12 @@ static void elroy_reset(DeviceState *dev) } } =20 +static void elroy_pcihost_instance_init(Object *obj) +{ + object_property_set_bool(obj, "config-reg-check-high-bit", false, + &error_fatal); +} + static void elroy_pcihost_realize(DeviceState *dev, Error **errp) { ElroyState *s =3D ELROY_PCI_HOST_BRIDGE(dev); @@ -440,7 +420,7 @@ static void elroy_pcihost_realize(DeviceState *dev, Err= or **errp) &elroy_config_addr_ops, dev, "pci-conf-idx", 8); memory_region_init_io(&phb->data_mem, obj, - &elroy_config_data_ops, dev, + &pci_host_data_le_ops, dev, "pci-conf-data", 8); memory_region_add_subregion(&s->this_mem, 0x40, &phb->conf_mem); @@ -497,6 +477,7 @@ static const TypeInfo elroy_pcihost_info =3D { .name =3D TYPE_ELROY_PCI_HOST_BRIDGE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(ElroyState), + .instance_init =3D elroy_pcihost_instance_init, .class_init =3D elroy_pcihost_class_init, }; =20 diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index a6fd88c2c46..792ab25729b 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -76,7 +76,5 @@ astro_chip_read(uint64_t addr, int size, uint64_t val) "a= ddr 0x%"PRIx64" size %d astro_chip_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" = size %d val 0x%"PRIx64 elroy_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %= d val 0x%"PRIx64 elroy_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size = %d val 0x%"PRIx64 -elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x= %"PRIx64" size %d val 0x%"PRIx64 -elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0= x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select= 0x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select = 0x%"PRIx64" size %d val 0x%"PRIx64 --=20 2.51.0 From nobody Fri Nov 14 18:15:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/4] hw/pci-host/dino: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 14:30:36 +0100 Message-ID: <20251027133037.70487-4-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761572065060154100 Avoid duplicating code, clear the "config-reg-check-high-bit" property in .instance_init() in order to re-use the generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/dino.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c index 924053499c1..e317167dbfa 100644 --- a/hw/pci-host/dino.c +++ b/hw/pci-host/dino.c @@ -302,27 +302,6 @@ static const VMStateDescription vmstate_dino =3D { } }; =20 -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. = */ - -static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned = len) -{ - PCIHostState *s =3D opaque; - return pci_data_read(s->bus, s->config_reg | (addr & 3), len); -} - -static void dino_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s =3D opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); -} - -static const MemoryRegionOps dino_config_data_ops =3D { - .read =3D dino_config_data_read, - .write =3D dino_config_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned = len) { DinoState *s =3D opaque; @@ -410,6 +389,12 @@ static void dino_pcihost_reset(DeviceState *dev) s->toc_addr =3D 0xFFFA0030; /* IO_COMMAND of CPU */ } =20 +static void dino_pcihost_instance_init(Object *obj) +{ + object_property_set_bool(obj, "config-reg-check-high-bit", false, + &error_fatal); +} + static void dino_pcihost_realize(DeviceState *dev, Error **errp) { DinoState *s =3D DINO_PCI_HOST_BRIDGE(dev); @@ -424,7 +409,7 @@ static void dino_pcihost_realize(DeviceState *dev, Erro= r **errp) &dino_config_addr_ops, DEVICE(s), "pci-conf-idx", 4); memory_region_init_io(&phb->data_mem, OBJECT(phb), - &dino_config_data_ops, DEVICE(s), + &pci_host_data_le_ops, DEVICE(s), "pci-conf-data", 4); memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, &phb->conf_mem); @@ -505,6 +490,7 @@ static const TypeInfo dino_pcihost_info =3D { .name =3D TYPE_DINO_PCI_HOST_BRIDGE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(DinoState), + .instance_init =3D dino_pcihost_instance_init, .class_init =3D dino_pcihost_class_init, }; =20 --=20 2.51.0 From nobody Fri Nov 14 18:15:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1761572115; cv=none; d=zohomail.com; s=zohoarc; b=G3hjFp6mYQh/c8/R5dGjm3C0xX3Dzw9vtDaiIe5MPUKccCrVDbGj96Ueqm1hX35vSWH6SEnx4Khh6E743gf+5yTRssMUbALKmv58d5cMLTI30qHUkilUfl0L7AkD7Y+9m1f6rrUo/OWP3eM8LQdQ/Bocre5DNWVRffGIImHG6Ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761572115; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TzCv5oKALadzAwWmhxHmfCNCg4IWePEaMyvXQSgNH0M=; b=FlvEjbx8DZ8MSrU3HJnVN63qWk45mMMkgOaHk0qqYM2/tb7fmcJyX+4PL1+GSWMFBT8Q29drFiluImAzwmyHowM0W0JIotXBnxS+Tf/PqGrC3FjJRen8ZAFci8xr/WJdcV3+x9F9fcXB/WtkPS/pqNc8c6/6rx9B9tkXoqiagqI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761572115425466.56020366208327; Mon, 27 Oct 2025 06:35:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDNMM-0007vS-Es; Mon, 27 Oct 2025 09:34:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDNLI-0007fM-J3 for qemu-devel@nongnu.org; Mon, 27 Oct 2025 09:33:17 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vDNLF-0006fc-4Y for qemu-devel@nongnu.org; Mon, 27 Oct 2025 09:33:00 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3ecdf2b1751so3236743f8f.0 for ; Mon, 27 Oct 2025 06:32:55 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/4] hw/pci-host/sabre: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 14:30:37 +0100 Message-ID: <20251027133037.70487-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761572118630158500 Avoid duplicating code, re-use the generic generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/sabre.c | 34 +++------------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 3 insertions(+), 33 deletions(-) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f95e5db583a..cc7229025f6 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -246,28 +246,6 @@ static const MemoryRegionOps sabre_config_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void sabre_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - SabreState *s =3D opaque; - PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - - trace_sabre_pci_config_write(addr, val); - pci_data_write(phb->bus, addr, val, size); -} - -static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, - unsigned size) -{ - uint32_t ret; - SabreState *s =3D opaque; - PCIHostState *phb =3D PCI_HOST_BRIDGE(s); - - ret =3D pci_data_read(phb->bus, addr, size); - trace_sabre_pci_config_read(addr, ret); - return ret; -} - /* The sabre host has an IRQ line for each IRQ line of each slot. */ static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { @@ -361,12 +339,6 @@ static void sabre_reset(DeviceState *d) pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); } =20 -static const MemoryRegionOps pci_config_ops =3D { - .read =3D sabre_pci_config_read, - .write =3D sabre_pci_config_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void sabre_realize(DeviceState *dev, Error **errp) { SabreState *s =3D SABRE(dev); @@ -430,12 +402,12 @@ static void sabre_init(Object *obj) =20 /* sabre_config */ memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, = s, - "sabre-config", 0x10000); + "pci-conf-idx", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->sabre_config); =20 - memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "sabre-pci-config", 0x1000000); + memory_region_init_io(&s->pci_config, OBJECT(s), &pci_host_data_le_ops= , s, + "pci-data-idx", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); =20 diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 792ab25729b..20c3cae47a2 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -35,8 +35,6 @@ sabre_set_request(int irq_num) "request irq %d" sabre_clear_request(int irq_num) "clear request irq %d" sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"= PRIx64 sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"P= RIx64 -sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val = 0x%"PRIx64 -sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0= x%"PRIx64 sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" =20 --=20 2.51.0