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Mon, 27 Oct 2025 03:09:43 -0700 (PDT) From: Michael Levit To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pbonzini@redhat.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com, smishash@gmail.com Subject: [PATCH v2 2/5] hw/misc: add NEORV32 SYSINFO block (CLK/MISC/SOC/CACHE) Date: Mon, 27 Oct 2025 12:09:35 +0200 Message-ID: <20251027100938.11822-3-michael@videogpu.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251027100938.11822-1-michael@videogpu.com> References: <20251027100938.11822-1-michael@videogpu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2a00:1450:4864:20::331; envelope-from=michael@videogpu.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @videogpu-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1761559879153158500 Content-Type: text/plain; charset="utf-8" From: Michael Add a minimal SYSINFO MMIO device compatible with NEORV32 SDK expectations: CLK (rw), MISC/SOC/CACHE (ro) composed from constants. Includes Kconfig/mes= on. Signed-off-by: Michael Levit diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 4e35657468..3de644a9e0 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -235,4 +235,6 @@ config IOSB config XLNX_VERSAL_TRNG bool =20 +config NEORV32_SYSINFO_QEMU + bool source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..4ea46ec2d1 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -34,6 +34,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: file= s('sifive_e_prci.c')) system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) +system_ss.add(when: 'CONFIG_NEORV32_SYSINFO_QEMU', if_true: files('neorv32= _sysinfo.c')) =20 subdir('macio') diff --git a/hw/misc/neorv32_sysinfo.c b/hw/misc/neorv32_sysinfo.c new file mode 100644 index 0000000000..09378b17a9 --- /dev/null +++ b/hw/misc/neorv32_sysinfo.c @@ -0,0 +1,183 @@ +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "system/address-spaces.h" +#include "neorv32_sysinfo.h" /* QEMU related */ +#include "neorv32_sysinfo_rtl.h" /* RTL related */ + + +/* Register addresses (offsets) */ +enum { + REG_SYSINFO_CLK =3D 0x00, + REG_SYSINFO_MISC =3D 0x04, + REG_SYSINFO_SOC =3D 0x08, + REG_SYSINFO_CACHE =3D 0x0C, +}; + + +typedef struct Neorv32SysInfoState { + MemoryRegion mmio; + uint32_t clk_hz; /* rw */ + uint32_t misc; /* ro */ + uint32_t soc; /* ro */ + uint32_t cache; /* ro */ +} Neorv32SysInfoState; + + +/* Safe integer log2: assumes power-of-two sizes; returns 0 if size is 0 */ +static unsigned int neorv32_log2u(uint32_t x) +{ + if (x =3D=3D 0U) { + return 0U; + } + unsigned int r =3D 0U; + while ((x >>=3D 1U) !=3D 0U) { + r++; + } + return r; +} + +/* Compose MISC register per the firmware header */ +static uint32_t neorv32_sysinfo_build_misc(void) +{ + const uint32_t imem_log2 =3D neorv32_log2u(SYSINFO_IMEM_SIZE) & 0xFFU= ; /* [7:0] */ + const uint32_t dmem_log2 =3D neorv32_log2u(SYSINFO_DMEM_SIZE) & 0xFFU= ; /* [15:8] */ + const uint32_t harts =3D (SYSINFO_NUM_HARTS & 0x0FU); = /* [19:16] */ + const uint32_t bootmode =3D (SYSINFO_BOOTMODE_ID & 0x03U); = /* [21:20] */ + const uint32_t intbus_to =3D (SYSINFO_INTBUS_TO_LOG2 & 0x1FU); = /* [26:22] */ + const uint32_t extbus_to =3D (SYSINFO_EXTBUS_TO_LOG2 & 0x1FU); = /* [31:27] */ + + uint32_t v =3D 0U; + v |=3D (imem_log2 << 0); + v |=3D (dmem_log2 << 8); + v |=3D (harts << 16); + v |=3D (bootmode << 20); + v |=3D (intbus_to << 22); + v |=3D (extbus_to << 27); + return v; +} + +/* Compose CACHE register per the firmware header */ +static uint32_t neorv32_sysinfo_build_cache(void) +{ + uint32_t v =3D 0U; + v |=3D ((ICACHE_BLOCK_SIZE_LOG2 & 0x0FU) << 0); + v |=3D ((ICACHE_NUM_BLOCKS_LOG2 & 0x0FU) << 4); + v |=3D ((DCACHE_BLOCK_SIZE_LOG2 & 0x0FU) << 8); + v |=3D ((DCACHE_NUM_BLOCKS_LOG2 & 0x0FU) << 12); + v |=3D ((ICACHE_BURSTS_EN ? 1U : 0U) << 16); + v |=3D ((DCACHE_BURSTS_EN ? 1U : 0U) << 24); + return v; +} + +static uint64_t neorv32_sysinfo_read(void *opaque, hwaddr addr, unsigned s= ize) +{ + Neorv32SysInfoState *s =3D opaque; + uint32_t val =3D 0U; + + switch (addr) { + case REG_SYSINFO_CLK: + val =3D s->clk_hz; + break; + case REG_SYSINFO_MISC: + val =3D s->misc; + break; + case REG_SYSINFO_SOC: + val =3D s->soc; + break; + case REG_SYSINFO_CACHE: + val =3D s->cache; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid read addr=3D0x%" HWADDR_PRIx " size=3D%= u\n", + __func__, addr, size); + return 0; + } + + /* Enforce access size semantics (1/2/4 ok); we just return the low by= tes */ + switch (size) { + case 4: return val; + case 2: return (uint16_t)val; + case 1: return (uint8_t)val; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid read size=3D%u at addr=3D0x%" HWADDR_PR= Ix "\n", + __func__, size, addr); + return 0; + } +} + +static void neorv32_sysinfo_write(void *opaque, hwaddr addr, uint64_t data= , unsigned size) +{ + Neorv32SysInfoState *s =3D opaque; + + /* Only CLK is writable; others are read-only */ + if (addr =3D=3D REG_SYSINFO_CLK) { + /* Accept 1/2/4 byte writes; update the corresponding bytes of clk= _hz */ + uint32_t old =3D s->clk_hz; + uint32_t val =3D old; + + switch (size) { + case 4: + val =3D (uint32_t)data; + break; + case 2: { + uint16_t part =3D (uint16_t)data; + /* Little-endian halfword at offset (0 or 2) */ + if ((addr & 0x3) =3D=3D 0x0) { + val =3D (old & 0xFFFF0000U) | part; + } else if ((addr & 0x3) =3D=3D 0x2) { + val =3D (old & 0x0000FFFFU) | ((uint32_t)part << 16); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: misaligned 16-bit write at 0x%" HWADDR_= PRIx "\n", + __func__, addr); + return; + } + break; + } + case 1: { + uint8_t part =3D (uint8_t)data; + uint32_t shift =3D (addr & 0x3) * 8U; + val =3D (old & ~(0xFFU << shift)) | ((uint32_t)part << shift); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write size=3D%u at addr=3D0x%" HWAD= DR_PRIx "\n", + __func__, size, addr); + return; + } + + s->clk_hz =3D val; + return; + } + + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only addr=3D0x%" HWADDR_PRIx " val=3D= 0x%" PRIx64 " size=3D%u\n", + __func__, addr, data, size); +} + +static const MemoryRegionOps neorv32_sysinfo_ops =3D { + .read =3D neorv32_sysinfo_read, + .write =3D neorv32_sysinfo_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +void neorv32_sysinfo_create(MemoryRegion *address_space, hwaddr base) +{ + Neorv32SysInfoState *s =3D g_new0(Neorv32SysInfoState, 1); + + s->clk_hz =3D SYSINFO_CLK_HZ_DEFAULT; + s->misc =3D neorv32_sysinfo_build_misc(); + s->soc =3D SYSINFO_SOC_VAL; + s->cache =3D neorv32_sysinfo_build_cache(); + + memory_region_init_io(&s->mmio, NULL, &neorv32_sysinfo_ops, + s, "neorv32.sysinfo", 16 /* 4 regs x 4 bytes */); + + memory_region_add_subregion(address_space, base, &s->mmio); +} diff --git a/hw/misc/neorv32_sysinfo.h b/hw/misc/neorv32_sysinfo.h new file mode 100644 index 0000000000..c0ac7d87e4 --- /dev/null +++ b/hw/misc/neorv32_sysinfo.h @@ -0,0 +1,79 @@ +#ifndef HW_NEORV32_SYSINFO_H +#define HW_NEORV32_SYSINFO_H + +#include "system/memory.h" + + +/* Internal memory sizes (bytes) */ +#define SYSINFO_IMEM_SIZE 0x00008000U /* 32 KiB IMEM */ +#define SYSINFO_DMEM_SIZE 0x00008000U /* 32 KiB DMEM */ + +/* Number of harts (physical cores) */ +#define SYSINFO_NUM_HARTS 1U + +/* Boot mode (matches RTL BOOT_MODE_SELECT encoding used in your firmware)= */ +#define SYSINFO_BOOTMODE_ID 0U /* 0..3 */ + +/* Bus timeout encodings: value is log2(cycles); 0 means "no timeout" per = your helper */ +#define SYSINFO_INTBUS_TO_LOG2 0U /* 0 =3D> returns 0 */ +#define SYSINFO_EXTBUS_TO_LOG2 0U /* 0 =3D> returns 0 */ + +/* Clock (Hz): writable at runtime via SYSINFO.CLK */ +#define SYSINFO_CLK_HZ_DEFAULT 100000000U /* 100 MHz */ + +/* Cache topology encodings (log2 values ) */ +#define ICACHE_BLOCK_SIZE_LOG2 0U /* bits [3:0] */ +#define ICACHE_NUM_BLOCKS_LOG2 0U /* bits [7:4] */ +#define DCACHE_BLOCK_SIZE_LOG2 0U /* bits [11:8] */ +#define DCACHE_NUM_BLOCKS_LOG2 0U /* bits [15:12] */ +#define ICACHE_BURSTS_EN 0U /* bit 16 */ +#define DCACHE_BURSTS_EN 0U /* bit 24 */ + +/* Feature bitmap for SOC register. */ +#define SYSINFO_SOC_ENABLE(x) (1U << (x)) + +// Enable Bootloader, IMEM, DMEM, UART and SPI +#define SYSINFO_SOC_VAL \ + ( SYSINFO_SOC_ENABLE(SYSINFO_SOC_BOOTLOADER) | \ + SYSINFO_SOC_ENABLE(SYSINFO_SOC_IMEM) | \ + SYSINFO_SOC_ENABLE(SYSINFO_SOC_DMEM) | \ + SYSINFO_SOC_ENABLE(SYSINFO_SOC_IO_UART0) | \ + SYSINFO_SOC_ENABLE(SYSINFO_SOC_IO_SPI) ) + +/* -----------------------------------------------------------------------= --------------- + * Address map + * -----------------------------------------------------------------------= -------------*/ +#define NEORV32_BOOTLOADER_BASE_ADDRESS (0xFFE00000U) +#define NEORV32_IO_BASE_ADDRESS (0xFFE00000U) + +#define NEORV32_IMEM_BASE (0x00000000U) +#define NEORV32_DMEM_BASE (0x80000000U) + +/* IO base addresses */ +#define NEORV32_TWD_BASE (0xFFEA0000U) +#define NEORV32_CFS_BASE (0xFFEB0000U) +#define NEORV32_SLINK_BASE (0xFFEC0000U) +#define NEORV32_DMA_BASE (0xFFED0000U) +#define NEORV32_CRC_BASE (0xFFEE0000U) +#define NEORV32_XIP_BASE (0xFFEF0000U) +#define NEORV32_PWM_BASE (0xFFF00000U) +#define NEORV32_GPTMR_BASE (0xFFF10000U) +#define NEORV32_ONEWIRE_BASE (0xFFF20000U) +#define NEORV32_XIRQ_BASE (0xFFF30000U) +#define NEORV32_MTIME_BASE (0xFFF40000U) +#define NEORV32_UART0_BASE (0xFFF50000U) +#define NEORV32_UART1_BASE (0xFFF60000U) +#define NEORV32_SDI_BASE (0xFFF70000U) +#define NEORV32_SPI_BASE (0xFFF80000U) +#define NEORV32_TWI_BASE (0xFFF90000U) +#define NEORV32_TRNG_BASE (0xFFFA0000U) +#define NEORV32_WDT_BASE (0xFFFB0000U) +#define NEORV32_GPIO_BASE (0xFFFC0000U) +#define NEORV32_NEOLED_BASE (0xFFFD0000U) +#define NEORV32_SYSINFO_BASE (0xFFFE0000U) +#define NEORV32_DM_BASE (0xFFFF0000U) + +/* MMIO creator */ +void neorv32_sysinfo_create(MemoryRegion *address_space, hwaddr base); + +#endif //HW_NEORV32_SYSINFO_H diff --git a/hw/misc/neorv32_sysinfo_rtl.h b/hw/misc/neorv32_sysinfo_rtl.h new file mode 100644 index 0000000000..594e251c5b --- /dev/null +++ b/hw/misc/neorv32_sysinfo_rtl.h @@ -0,0 +1,134 @@ +// #######################################################################= ########################## +// # << NEORV32: neorv32_sysinfo.h - System Information Memory (SYSINFO) H= W Driver >> # +// # *********************************************************************= ************************ # +// # BSD 3-Clause License = # +// # = # +// # Copyright (c) 2023, Stephan Nolting. All rights reserved. = # +// # = # +// # Redistribution and use in source and binary forms, with or without mo= dification, are # +// # permitted provided that the following conditions are met: = # +// # = # +// # 1. Redistributions of source code must retain the above copyright not= ice, this list of # +// # conditions and the following disclaimer. = # +// # = # +// # 2. Redistributions in binary form must reproduce the above copyright = notice, this list of # +// # conditions and the following disclaimer in the documentation and/o= r other materials # +// # provided with the distribution. = # +// # = # +// # 3. Neither the name of the copyright holder nor the names of its cont= ributors may be used to # +// # endorse or promote products derived from this software without spe= cific prior written # +// # permission. = # +// # = # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "= AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR= RANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. = IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, = INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, P= ROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRU= PTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY= , OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SO= FTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. = # +// # *********************************************************************= ************************ # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 = (c) Stephan Nolting # +// #######################################################################= ########################## + + +/**********************************************************************//** + * @file neorv32_cfs.h + * @brief System Configuration Information Memory (SYSINFO) HW driver head= er file. + *************************************************************************= */ + +#ifndef neorv32_sysinfo_h +#define neorv32_sysinfo_h + +/**********************************************************************//** + * @name IO Device: System Configuration Information Memory (SYSINFO) + *************************************************************************= */ +/**@{*/ +/** SYSINFO module prototype - whole module is read-only */ +typedef volatile struct __attribute__((packed,aligned(4))) { + uint32_t CLK; /**< offset 0: Clock speed in Hz */ + const uint32_t MISC; /**< offset 4: Miscellaneous system configuration= s (#NEORV32_SYSINFO_MISC_enum) */ + const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC= _enum) */ + const uint32_t CACHE; /**< offset 12: Cache configuration (#NEORV32_SYSI= NFO_CACHE_enum) */ +} neorv32_sysinfo_t; + +/** SYSINFO module hardware access (#neorv32_sysinfo_t) */ +#define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)) + +/** NEORV32_SYSINFO.MISC (r/-): Miscellaneous system configurations */ +enum NEORV32_SYSINFO_MISC_enum { + SYSINFO_MISC_IMEM_LSB =3D 0, /**< SYSINFO_MISC (0) (r/-): log2(interna= l IMEM size in bytes) (via IMEM_SIZE generic), LSB */ + SYSINFO_MISC_IMEM_MBS =3D 7, /**< SYSINFO_MISC (7) (r/-): log2(interna= l IMEM size in bytes) (via IMEM_SIZE generic), MSB */ + + SYSINFO_MISC_DMEM_LSB =3D 8, /**< SYSINFO_MISC (8) (r/-): log2(interna= l DMEM size in bytes) (via DMEM_SIZE generic), LSB */ + SYSINFO_MISC_DMEM_MSB =3D 15, /**< SYSINFO_MISC (15) (r/-): log2(interna= l DMEM size in bytes) (via DMEM_SIZE generic), MSB */ + + SYSINFO_MISC_HART_LSB =3D 16, /**< SYSINFO_MISC (16) (r/-): number of ph= ysical CPU cores ("harts"), LSB */ + SYSINFO_MISC_HART_MSB =3D 19, /**< SYSINFO_MISC (19) (r/-): number of ph= ysical CPU cores ("harts"), MSB */ + + SYSINFO_MISC_BOOT_LSB =3D 20, /**< SYSINFO_MISC (20) (r/-): boot mode co= nfiguration (via BOOT_MODE_SELECT generic), LSB */ + SYSINFO_MISC_BOOT_MSB =3D 21, /**< SYSINFO_MISC (21) (r/-): boot mode co= nfiguration (via BOOT_MODE_SELECT generic), MSB */ + + SYSINFO_MISC_ITMO_LSB =3D 22, /**< SYSINFO_MISC (22) (r/-): log2(interna= l bus timeout cycles), LSB */ + SYSINFO_MISC_ITMO_MSB =3D 26, /**< SYSINFO_MISC (26) (r/-): log2(interna= l bus timeout cycles), MSB */ + + SYSINFO_MISC_ETMO_LSB =3D 27, /**< SYSINFO_MISC (27) (r/-): log2(externa= l bus timeout cycles), LSB */ + SYSINFO_MISC_ETMO_MSB =3D 31 /**< SYSINFO_MISC (31) (r/-): log2(externa= l bus timeout cycles), MSB */ +}; + +/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */ +enum NEORV32_SYSINFO_SOC_enum { + SYSINFO_SOC_BOOTLOADER =3D 0, /**< SYSINFO_SOC (0) (r/-): Bootloader i= mplemented when 1 (via BOOT_MODE_SELECT generic) */ + SYSINFO_SOC_XBUS =3D 1, /**< SYSINFO_SOC (1) (r/-): External bus= interface implemented when 1 (via XBUS_EN generic) */ + SYSINFO_SOC_IMEM =3D 2, /**< SYSINFO_SOC (2) (r/-): Processor-in= ternal instruction memory implemented when 1 (via IMEM_EN generic) */ + SYSINFO_SOC_DMEM =3D 3, /**< SYSINFO_SOC (3) (r/-): Processor-in= ternal data memory implemented when 1 (via DMEM_EN generic) */ + SYSINFO_SOC_OCD =3D 4, /**< SYSINFO_SOC (4) (r/-): On-chip debu= gger implemented when 1 (via OCD_EN generic) */ + SYSINFO_SOC_ICACHE =3D 5, /**< SYSINFO_SOC (5) (r/-): Processor-in= ternal instruction cache implemented when 1 (via ICACHE_EN generic) */ + SYSINFO_SOC_DCACHE =3D 6, /**< SYSINFO_SOC (6) (r/-): Processor-in= ternal instruction cache implemented when 1 (via DCACHE_EN generic) */ +//SYSINFO_SOC_reserved =3D 7, /**< SYSINFO_SOC (7) (r/-): reserved */ +//SYSINFO_SOC_reserved =3D 8, /**< SYSINFO_SOC (8) (r/-): reserved */ +//SYSINFO_SOC_reserved =3D 9, /**< SYSINFO_SOC (9) (r/-): reserved */ +//SYSINFO_SOC_reserved =3D 10, /**< SYSINFO_SOC (10) (r/-): reserved */ + SYSINFO_SOC_OCD_AUTH =3D 11, /**< SYSINFO_SOC (11) (r/-): On-chip debu= gger authentication implemented when 1 (via OCD_AUTHENTICATION generic) */ + SYSINFO_SOC_IMEM_ROM =3D 12, /**< SYSINFO_SOC (12) (r/-): Processor-in= ternal instruction memory implemented as pre-initialized ROM when 1 (via BO= OT_MODE_SELECT generic) */ + SYSINFO_SOC_IO_TWD =3D 13, /**< SYSINFO_SOC (13) (r/-): Two-wire dev= ice implemented when 1 (via IO_TWD_EN generic) */ + SYSINFO_SOC_IO_DMA =3D 14, /**< SYSINFO_SOC (14) (r/-): Direct memor= y access controller implemented when 1 (via IO_DMA_EN generic) */ + SYSINFO_SOC_IO_GPIO =3D 15, /**< SYSINFO_SOC (15) (r/-): General purp= ose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */ + SYSINFO_SOC_IO_CLINT =3D 16, /**< SYSINFO_SOC (16) (r/-): Core local i= nterruptor implemented when 1 (via IO_CLINT_EN generic) */ + SYSINFO_SOC_IO_UART0 =3D 17, /**< SYSINFO_SOC (17) (r/-): Primary univ= ersal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_= EN generic) */ + SYSINFO_SOC_IO_SPI =3D 18, /**< SYSINFO_SOC (18) (r/-): Serial perip= heral interface implemented when 1 (via IO_SPI_EN generic) */ + SYSINFO_SOC_IO_TWI =3D 19, /**< SYSINFO_SOC (19) (r/-): Two-wire int= erface implemented when 1 (via IO_TWI_EN generic) */ + SYSINFO_SOC_IO_PWM =3D 20, /**< SYSINFO_SOC (20) (r/-): Pulse-width = modulation unit implemented when 1 (via IO_PWM_EN generic) */ + SYSINFO_SOC_IO_WDT =3D 21, /**< SYSINFO_SOC (21) (r/-): Watchdog tim= er implemented when 1 (via IO_WDT_EN generic) */ + SYSINFO_SOC_IO_CFS =3D 22, /**< SYSINFO_SOC (22) (r/-): Custom funct= ions subsystem implemented when 1 (via IO_CFS_EN generic) */ + SYSINFO_SOC_IO_TRNG =3D 23, /**< SYSINFO_SOC (23) (r/-): True random = number generator implemented when 1 (via IO_TRNG_EN generic) */ + SYSINFO_SOC_IO_SDI =3D 24, /**< SYSINFO_SOC (24) (r/-): Serial data = interface implemented when 1 (via IO_SDI_EN generic) */ + SYSINFO_SOC_IO_UART1 =3D 25, /**< SYSINFO_SOC (25) (r/-): Secondary un= iversal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART= 1_EN generic) */ + SYSINFO_SOC_IO_NEOLED =3D 26, /**< SYSINFO_SOC (26) (r/-): NeoPixel-com= patible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */ + SYSINFO_SOC_IO_TRACER =3D 27, /**< SYSINFO_SOC (10) (r/-): Execution tr= acer implemented when 1 (via IO_TRACER_EN generic) */ + SYSINFO_SOC_IO_GPTMR =3D 28, /**< SYSINFO_SOC (28) (r/-): General purp= ose timer implemented when 1 (via IO_GPTMR_EN generic) */ + SYSINFO_SOC_IO_SLINK =3D 29, /**< SYSINFO_SOC (29) (r/-): Stream link = interface implemented when 1 (via IO_SLINK_EN generic) */ + SYSINFO_SOC_IO_ONEWIRE =3D 30 /**< SYSINFO_SOC (30) (r/-): 1-wire inter= face controller implemented when 1 (via IO_ONEWIRE_EN generic) */ +//SYSINFO_SOC_reserved =3D 31 /**< SYSINFO_SOC (31) (r/-): reserved */ +}; + +/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */ + enum NEORV32_SYSINFO_CACHE_enum { + SYSINFO_CACHE_INST_BLOCK_SIZE_0 =3D 0, /**< SYSINFO_CACHE (0) (r/-): i= -cache: log2(Block size in bytes), bit 0 (via CACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_INST_BLOCK_SIZE_3 =3D 3, /**< SYSINFO_CACHE (3) (r/-): i= -cache: log2(Block size in bytes), bit 3 (via CACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_INST_NUM_BLOCKS_0 =3D 4, /**< SYSINFO_CACHE (4) (r/-): i= -cache: log2(Number of cache blocks), bit 0 (via ICACHE_NUM_BLOCKS generic)= */ + SYSINFO_CACHE_INST_NUM_BLOCKS_3 =3D 7, /**< SYSINFO_CACHE (7) (r/-): i= -cache: log2(Number of cache blocks), bit 3 (via ICACHE_NUM_BLOCKS generic)= */ + + SYSINFO_CACHE_DATA_BLOCK_SIZE_0 =3D 8, /**< SYSINFO_CACHE (8) (r/-): d= -cache: log2(Block size in bytes), bit 0 (via CACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_DATA_BLOCK_SIZE_3 =3D 11, /**< SYSINFO_CACHE (11) (r/-): d= -cache: log2(Block size in bytes), bit 3 (via CACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_DATA_NUM_BLOCKS_0 =3D 12, /**< SYSINFO_CACHE (12) (r/-): d= -cache: log2(Number of cache blocks), bit 0 (via DCACHE_NUM_BLOCKS generic)= */ + SYSINFO_CACHE_DATA_NUM_BLOCKS_3 =3D 15, /**< SYSINFO_CACHE (15) (r/-): d= -cache: log2(Number of cache blocks), bit 3 (via DCACHE_NUM_BLOCKS generic)= */ + + SYSINFO_CACHE_INST_BURSTS_EN =3D 16, /**< SYSINFO_CACHE (16) (r/-): i= -cache: issue burst transfers or cache update (via CACHE_BURSTS_EN generic)= */ + SYSINFO_CACHE_DATA_BURSTS_EN =3D 24 /**< SYSINFO_CACHE (14) (r/-): d= -cache: issue burst transfers or cache update (via CACHE_BURSTS_EN generic)= */ +}; +/**@}*/ + + +#endif // neorv32_sysinfo_h