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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1761568425913154100 Signed-off-by: Anton Johansson --- include/hw/riscv/boot.h | 20 ++++++++++---------- hw/riscv/boot.c | 22 +++++++++++----------- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 2 +- 6 files changed, 26 insertions(+), 26 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7d59b2e6c6..d835594baa 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,21 +43,21 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); =20 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr); -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firm= ware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr); +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); char *riscv_find_firmware(const char *firmware_filename, const char *default_machine_firmware); -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 828a867be3..4eadcff26c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartA= rrayState *harts) info->is_32bit =3D riscv_is_32bit(harts); } =20 -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr) { +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr) { if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { @@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filena= me, return filename; } =20 -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firm= ware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename; - target_ulong firmware_end_addr =3D *firmware_load_addr; + hwaddr firmware_end_addr =3D *firmware_load_addr; =20 firmware_filename =3D riscv_find_firmware(machine->firmware, default_machine_firmware); @@ -154,9 +154,9 @@ target_ulong riscv_find_and_load_firmware(MachineState = *machine, return firmware_end_addr; } =20 -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { uint64_t firmware_entry, firmware_end; ssize_t firmware_size; @@ -227,7 +227,7 @@ static void riscv_load_initrd(MachineState *machine, RI= SCVBootInfo *info) =20 void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) { diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2e74783fce..e5a0196a00 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -515,7 +515,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) uint64_t mem_low_size, mem_high_size; hwaddr firmware_load_addr; const char *firmware_name; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; uint64_t fdt_load_addr; DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d69f942cfb..390f9b8d9a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -515,7 +515,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); hwaddr start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; const char *firmware_name; uint32_t start_addr_hi32 =3D 0x00000000; uint32_t fdt_load_addr_hi32 =3D 0x00000000; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 641aae8c01..b0bab3fe00 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -197,9 +197,9 @@ static void spike_board_init(MachineState *machine) SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - target_ulong firmware_end_addr =3D memmap[SPIKE_DRAM].base; + hwaddr firmware_end_addr =3D memmap[SPIKE_DRAM].base; hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base; - target_ulong kernel_start_addr; + hwaddr kernel_start_addr; char *firmware_name; uint64_t fdt_load_addr; uint64_t kernel_entry; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 47e573f85a..17909206c7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1434,7 +1434,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; + hwaddr firmware_end_addr, kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); uint64_t fdt_load_addr; uint64_t kernel_entry =3D 0; --=20 2.51.0 From nobody Fri Nov 14 18:15:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1761568573011158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 6 ++++-- hw/riscv/riscv_hart.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index b33c7fe325..f8656ec04b 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -26,6 +26,8 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/timer.h" +#include "qemu/target-info.h" +#include "qemu/bitops.h" =20 #include "cpu_bits.h" #include "riscv-iommu.h" @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx, const uint64_t va_mask =3D (1ULL << va_len) - 1; =20 if (pass =3D=3D S_STAGE && va_len > 32) { - target_ulong mask, masked_msbs; + uint64_t mask, masked_msbs; =20 - mask =3D (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1; + mask =3D MAKE_64BIT_MASK(0, target_long_bits() - va_len + = 1); masked_msbs =3D (addr >> (va_len - 1)) & mask; =20 if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index c7e98a4308..65d2c92018 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **= words) g_assert(rc =3D=3D 0); csr_call(words[1], cpu, csr, &val); =20 - qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); + qtest_sendf(chr, "OK 0 %"PRIx64"\n", val); =20 return true; } --=20 2.51.0 From nobody Fri Nov 14 18:15:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761568427051374.87961941964136; Mon, 27 Oct 2025 05:33:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDMPJ-0000DL-8i; Mon, 27 Oct 2025 08:33:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDMOn-0008K2-Vp for qemu-devel@nongnu.org; Mon, 27 Oct 2025 08:32:38 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDMOh-0005Qt-O2 for qemu-devel@nongnu.org; Mon, 27 Oct 2025 08:32:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=wFCezcQ7fh5qeB/Zli5cwGtrrz+6fzqC0Kwv+DN1bYU=; b=vCe0LAtTgZhyv01 unEaIJVM57xZxZBaj5DIK96qR94w2TcqIImi/lsB9kDdo3MpxnUzPAVz/0YlQcpMQzWiOTSzahdw2 xS+Fps2dQ3/n69Hqs2WmWixKyO5hdzkMK9tDOH2TtAFVUxHvptbAJ+bml0kmUZ/Vj5dkcdW7w6/Mu RI=; Date: Mon, 27 Oct 2025 13:35:12 +0100 Subject: [PATCH v2 3/3] hw/riscv: Widen OpenSBI dynamic info struct MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-feature-single-binary-hw-v1-v2-3-44478d589ae9@rev.ng> References: <20251027-feature-single-binary-hw-v1-v2-0-44478d589ae9@rev.ng> In-Reply-To: <20251027-feature-single-binary-hw-v1-v2-0-44478d589ae9@rev.ng> To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, richard.henderson@linaro.org, palmer@dabbelt.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1761568429006158500 Since fw_dynamic_info is only used for non 32 bit targets, target_long is int64_t anyway. Rename struct to fw_dynamic_info64 and use int64_t. Reviewed-by: Alistair Francis Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/boot_opensbi.h | 14 +++++++------- hw/riscv/boot.c | 22 ++++++++++++---------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensb= i.h index 18664a174b..ab9999be3f 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -29,17 +29,17 @@ enum sbi_scratch_options { }; =20 /** Representation dynamic info passed by previous booting stage */ -struct fw_dynamic_info { +struct fw_dynamic_info64 { /** Info magic */ - target_long magic; + int64_t magic; /** Info version */ - target_long version; + int64_t version; /** Next booting stage address */ - target_long next_addr; + int64_t next_addr; /** Next booting stage mode */ - target_long next_mode; + int64_t next_mode; /** Options for OpenSBI library */ - target_long options; + int64_t options; /** * Preferred boot HART id * @@ -55,7 +55,7 @@ struct fw_dynamic_info { * stage can set it to -1UL which will force the FW_DYNAMIC firmware * to use the relocation lottery mechanism. */ - target_long boot_hart; + int64_t boot_hart; }; =20 /** Representation dynamic info passed by previous booting stage */ diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4eadcff26c..64608e58c7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -387,7 +387,8 @@ void riscv_rom_copy_firmware_info(MachineState *machine, uint64_t kernel_entry) { struct fw_dynamic_info32 dinfo32; - struct fw_dynamic_info dinfo; + struct fw_dynamic_info64 dinfo64; + void *dinfo_ptr =3D NULL; size_t dinfo_len; =20 if (riscv_is_32bit(harts)) { @@ -397,15 +398,17 @@ void riscv_rom_copy_firmware_info(MachineState *machi= ne, dinfo32.next_addr =3D cpu_to_le32(kernel_entry); dinfo32.options =3D 0; dinfo32.boot_hart =3D 0; + dinfo_ptr =3D &dinfo32; dinfo_len =3D sizeof(dinfo32); } else { - dinfo.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); - dinfo.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo.next_addr =3D cpu_to_le64(kernel_entry); - dinfo.options =3D 0; - dinfo.boot_hart =3D 0; - dinfo_len =3D sizeof(dinfo); + dinfo64.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo64.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); + dinfo64.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo64.next_addr =3D cpu_to_le64(kernel_entry); + dinfo64.options =3D 0; + dinfo64.boot_hart =3D 0; + dinfo_ptr =3D &dinfo64; + dinfo_len =3D sizeof(dinfo64); } =20 /** @@ -419,8 +422,7 @@ void riscv_rom_copy_firmware_info(MachineState *machine, } =20 rom_add_blob_fixed_as("mrom.finfo", - riscv_is_32bit(harts) ? - (void *)&dinfo32 : (void *)&dinfo, + dinfo_ptr, dinfo_len, rom_base + reset_vec_size, &address_space_memory); --=20 2.51.0