From nobody Mon Oct 27 14:12:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=rt-thread.org ARC-Seal: i=1; a=rsa-sha256; t=1761476487; cv=none; d=zohomail.com; s=zohoarc; b=HmN49d7tUVaTAZY314TW6hB88ICNAkFBQIXudAsuikiJz91RWJGNW1PRfFgziETh/phu8w2PJKS8MQaMyDACcbECTf6tc2fqiAIUkaOMptVkjv1/l5Jg78LeiQ/Ty3Y1ZRnuPqZKhPXvVJRp0wFZpIomSOKn6iUPnLAD2CR0UWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761476487; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OPeNH0YZQT3ge2lXtgrOwVZ7h5TGBUtzJOp/6Nywh3M=; b=P77VRB2V3xUR5MR7NoKpI2DzA9wFOWQYOgoLoYRQiZ7m44YhA7J5RWip+Lk0zhBvvt50ap8687Wugwg5yI4wv1wjDmbhhGI+UxFjp0g8/0tGcpBv5mqIFQgSkB/YH538AFG3yFLGxJ6mf2EDpsayAcOpyjJK4c0LNdDWtEJzSjI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761476487143284.0567270300172; Sun, 26 Oct 2025 04:01:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vCyUi-0000DM-Et; Sun, 26 Oct 2025 07:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vCyUX-0000C2-8Q for qemu-devel@nongnu.org; Sun, 26 Oct 2025 07:00:57 -0400 Received: from mail-m83244.xmail.ntesmail.com ([156.224.83.244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vCyUT-0001De-Ip for qemu-devel@nongnu.org; Sun, 26 Oct 2025 07:00:52 -0400 Received: from DESKTOP-FHFCVTH.localdomain (unknown [117.67.70.197]) by smtp.qiye.163.com (Hmail) with ESMTP id 2734efe93; Sun, 26 Oct 2025 18:53:33 +0800 (GMT+08:00) From: fanyihao@rt-thread.org To: qemu-devel@nongnu.org Cc: Peter Maydell , Yihao Fan Subject: [PATCH v3 3/3] hw/arm/stm32f407: Add PWR device to stm32f407 SoC Date: Sun, 26 Oct 2025 18:53:20 +0800 Message-ID: <20251026105320.5591-4-fanyihao@rt-thread.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026105320.5591-1-fanyihao@rt-thread.org> References: <20251026105320.5591-1-fanyihao@rt-thread.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9a2026ec0603a4kunmcecdce756fba16 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZT00ZVhgeGE1LHUxMQxpOHlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVTUxVTEtVSkJMWVdZFhoPEhUdFFlBWUtVS1VLVUtZBg++ DKIM-Signature: a=rsa-sha256; b=LeSv9dIE7r+kD8x2p89LehFf14dQXQWBwvEmfakyPeh38c6ZH+XKgvWp7uMYK28i9LbmZt2S3cn0JiXbmdvA3ZXgA6d4mm7NnPvmX9InGdkA2BmqwaiKDHSY/03wle9AfeIguSbZ/vVmRfsH5m0/5cg2J5oTFSd5PSuidZplT6D67RwUyySzL5KVLvB2j9U7gcY/MGZAzC7Gfg7qIeLhjERs0l6C0vBy/FYaf0jo1pjYH+zbq+MOX9ML6QqdqfYpQmwemsUiMvZmw9KCsKmRl4kFmOSZolT5QRt2sQDumqmxWo7nJBbkz5QovcYp748CUjkNWDmAUr6eYUl3k3PGYQ==; s=default; c=relaxed/relaxed; d=rt-thread.org; v=1; bh=OPeNH0YZQT3ge2lXtgrOwVZ7h5TGBUtzJOp/6Nywh3M=; h=date:mime-version:subject:message-id:from; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=156.224.83.244; envelope-from=fanyihao@rt-thread.org; helo=mail-m83244.xmail.ntesmail.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rt-thread.org) X-ZM-MESSAGEID: 1761476491559158500 Content-Type: text/plain; charset="utf-8" From: Yihao Fan Add the Power supply configuration device to the stm32f407 SoC. Signed-off-by: Yihao Fan --- docs/system/arm/stm32.rst | 1 + hw/arm/Kconfig | 1 + hw/arm/stm32f407_soc.c | 9 +++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/stm32f4xx_pwr.c | 111 ++++++++++++++++++++++++++++++++ include/hw/arm/stm32f407_soc.h | 3 + include/hw/misc/stm32f4xx_pwr.h | 40 ++++++++++++ 8 files changed, 169 insertions(+) create mode 100644 hw/misc/stm32f4xx_pwr.c create mode 100644 include/hw/misc/stm32f4xx_pwr.h diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index 3f085eb35ee..c83276f6c12 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -38,6 +38,7 @@ Supported devices * System configuration (SYSCFG) * Timer controller (TIMER) * Reset and Clock Controller (RCC) (STM32F4 only, reset and enable only) + * Power supply configuration (PWR) (STM32F4 only) =20 Missing devices --------------- diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ddb2da45ae9..2c07220eb0b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -417,6 +417,7 @@ config STM32F407_SOC select ARM_V7M select STM32F4XX_SYSCFG select STM32F4XX_EXTI + select STM32F4XX_PWR =20 config B_L475E_IOT01A bool diff --git a/hw/arm/stm32f407_soc.c b/hw/arm/stm32f407_soc.c index 8e20ddcd5b1..1512d922e5e 100644 --- a/hw/arm/stm32f407_soc.c +++ b/hw/arm/stm32f407_soc.c @@ -51,6 +51,7 @@ static void stm32f407_soc_initfn(Object *obj) object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSC= FG); object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC); + object_initialize_child(obj, "pwr", &s->pwr, TYPE_STM32F4XX_PWR); =20 for (i =3D 0; i < STM_NUM_USARTS; i++) { object_initialize_child(obj, "usart[*]", &s->usart[i], @@ -183,6 +184,14 @@ static void stm32f407_soc_realize(DeviceState *dev_soc= , Error **errp) sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i= ])); } =20 + /* PWR controller */ + dev =3D DEVICE(&s->pwr); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwr), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, PWR_BASE_ADDR); + } =20 static void stm32f407_soc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 4e35657468b..ff4dc58b4d3 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -108,6 +108,9 @@ config STM32F4XX_SYSCFG config STM32F4XX_EXTI bool =20 +config STM32F4XX_PWR + bool + config STM32L4X5_EXTI bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2a..0e0f5c3a275 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -112,6 +112,7 @@ system_ss.add(when: 'CONFIG_STM32_RCC', if_true: files(= 'stm32_rcc.c')) system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_s= yscfg.c')) system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_s= yscfg.c')) system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_ext= i.c')) +system_ss.add(when: 'CONFIG_STM32F4XX_PWR', if_true: files('stm32f4xx_pwr.= c')) system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_ext= i.c')) system_ss.add(when: 'CONFIG_STM32L4X5_SYSCFG', if_true: files('stm32l4x5_s= yscfg.c')) system_ss.add(when: 'CONFIG_STM32L4X5_RCC', if_true: files('stm32l4x5_rcc.= c')) diff --git a/hw/misc/stm32f4xx_pwr.c b/hw/misc/stm32f4xx_pwr.c new file mode 100644 index 00000000000..83ce0e6a0a9 --- /dev/null +++ b/hw/misc/stm32f4xx_pwr.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) liang yan + * Copyright (c) Yihao Fan + * The reference used is the STMicroElectronics RM0090 Reference manual + * https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417/do= cumentation.html + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/misc/stm32f4xx_pwr.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qemu/module.h" +#include "migration/vmstate.h" +#include "qemu/module.h" + +#ifndef STM32F4XX_PWR_DEBUG +#define STM32F4XX_PWR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM32F4XX_PWR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static uint64_t stm32f4xx_pwr_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + STM32F4XXPwrState *s =3D opaque; + + switch (offset) { + case PWR_CR: + return s->pwr_cr; + case PWR_CSR: + return s->pwr_csr; + default: + qemu_log_mask(LOG_GUEST_ERROR, "STM32F4XX PWR: Bad read offset 0x%= lx\n", offset); + return 0; + } +} + +static void stm32f4xx_pwr_write(void *opaque, hwaddr offset, uint64_t valu= e, unsigned size) +{ + STM32F4XXPwrState *s =3D opaque; + + switch (offset) { + case PWR_CR: + s->pwr_cr =3D value; + if (value & PWR_CR_ODEN) + s->pwr_csr |=3D PWR_CSR_ODRDY; + if (value & PWR_CR_ODSWEN) + s->pwr_csr |=3D PWR_CSR_ODSWRDY; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "STM32F4XX PWR: Bad write offset 0x= %lx\n", offset); + break; + } +} + +static const MemoryRegionOps stm32f4xx_pwr_ops =3D { + .read =3D stm32f4xx_pwr_read, + .write =3D stm32f4xx_pwr_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void stm32f4xx_pwr_init(Object *obj) +{ + STM32F4XXPwrState *s =3D STM32F4XX_PWR(obj); + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_pwr_ops, s, TYPE_STM32= F4XX_PWR, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void stm32f4xx_pwr_reset(DeviceState *dev) +{ + STM32F4XXPwrState *s =3D STM32F4XX_PWR(dev); + + s->pwr_cr =3D 0x0000; + s->pwr_csr =3D 0x0000; +} + +static void stm32f4xx_pwr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, stm32f4xx_pwr_reset); +} + +static const TypeInfo stm32f4xx_pwr_info =3D { + .name =3D TYPE_STM32F4XX_PWR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(STM32F4XXPwrState), + .instance_init =3D stm32f4xx_pwr_init, + .class_init =3D stm32f4xx_pwr_class_init, +}; + +static void stm32f4xx_pwr_register_types(void) +{ + type_register_static(&stm32f4xx_pwr_info); +} + +type_init(stm32f4xx_pwr_register_types) diff --git a/include/hw/arm/stm32f407_soc.h b/include/hw/arm/stm32f407_soc.h index 3497e91aa1c..f7e39ffaceb 100644 --- a/include/hw/arm/stm32f407_soc.h +++ b/include/hw/arm/stm32f407_soc.h @@ -17,6 +17,7 @@ #include "hw/char/stm32f2xx_usart.h" #include "hw/timer/stm32f2xx_timer.h" #include "hw/misc/stm32_rcc.h" +#include "hw/misc/stm32f4xx_pwr.h" #include "qom/object.h" =20 #define TYPE_STM32F407_SOC "stm32f407-soc" @@ -39,6 +40,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F407State, STM32F407_SOC) #define SYSCFG_BASE_ADDRESS 0x40013800 #define SYSCFG_IRQ 71 #define EXIT_BASE_ADDRESS 0x40013C00 +#define PWR_BASE_ADDR 0x40007000 =20 #define FLASH_BASE_ADDRESS 0x8000000 #define FLASH_SIZE 0x100000 @@ -57,6 +59,7 @@ typedef struct STM32F407State { STM32RccState rcc; STM32F4xxSyscfgState syscfg; STM32F4xxExtiState exti; + STM32F4XXPwrState pwr; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; =20 diff --git a/include/hw/misc/stm32f4xx_pwr.h b/include/hw/misc/stm32f4xx_pw= r.h new file mode 100644 index 00000000000..889fbc26ab0 --- /dev/null +++ b/include/hw/misc/stm32f4xx_pwr.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) liang yan + * Copyright (c) Yihao Fan + * The reference used is the STMicroElectronics RM0090 Reference manual + * https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417/do= cumentation.html + */ + +#ifndef STM32F4XX_PWR_H +#define STM32F4XX_PWR_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define PWR_CR 0x00 +#define PWR_CSR 0x04 + +#define PWR_CR_DBP (1 << 8) +#define PWR_CR_ODEN (1 << 16) +#define PWR_CR_ODSWEN (1 << 17) + +#define PWR_CSR_ODRDY (1 << 16) +#define PWR_CSR_ODSWRDY (1 << 17) + +#define TYPE_STM32F4XX_PWR "stm32f4xx-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(STM32F4XXPwrState, STM32F4XX_PWR) + +struct STM32F4XXPwrState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t pwr_cr; + uint32_t pwr_csr; +}; + +#endif --=20 2.43.0