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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761289059; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Knj5o0XKslR8KZibGSIwkm7pF6XSwQomEo4fnIU5PI8=; b=fVunw9/HArt65UPaUjO8H7lejxxffeAhmOX7qFpIhVEFX3NzcCa0B2Je1MbI6GZdWVkeSi gPKZVWwi7wtz+te5fzAdXsRVYzxuGkF5dk+BJw/qPtltgdA8XKQP0tlQuKtp3q8qt0HhS6 +r1K2ifdG+XOYEDAnSsSO5jSlNDgous= X-MC-Unique: m25K25NfP6GZe2m-AqMZ6Q-1 X-Mimecast-MFC-AGG-ID: m25K25NfP6GZe2m-AqMZ6Q_1761289054 From: Thomas Huth To: Nicholas Piggin , Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 1/2] target/ppc/cpu_init: Simplify the setup of the TLBxCFG SPR registers Date: Fri, 24 Oct 2025 08:57:25 +0200 Message-ID: <20251024065726.738005-2-thuth@redhat.com> In-Reply-To: <20251024065726.738005-1-thuth@redhat.com> References: <20251024065726.738005-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761289090061158500 From: Thomas Huth The next commit is going to remove init_proc_e200(), which is one of the two calling sites of register_BookE206_sprs(). This causes recent versions of GCC to inline the register_BookE206_sprs() function into the other only remaining calling site, init_proc_e500(), which in turn causes some false-positives compiler warnings: In file included from ../../devel/qemu/target/ppc/cpu_init.c:46: In function =E2=80=98register_BookE206_sprs=E2=80=99, inlined from =E2=80=98init_proc_e500=E2=80=99 at ../../devel/qemu/targ= et/ppc/cpu_init.c:2910:5: ../../devel/qemu/target/ppc/cpu_init.c:897:29: error: array subscript 3 is outside array bounds of =E2=80=98uint32_t[2]=E2=80= =99 {aka =E2=80=98unsigned int[2]=E2=80=99} [-Werror=3Darray-bounds=3D] 897 | tlbncfg[3]); | ~~~~~~~^~~ ../../devel/qemu/target/ppc/spr_common.h:61:39: note: in definition of mac= ro =E2=80=98spr_register_kvm_hv=E2=80=99 61 | KVM_ARG(one_reg_id) initial_value) | ^~~~~~~~~~~~~ ../../devel/qemu/target/ppc/spr_common.h:77:5: note: in expansion of macro= =E2=80=98spr_register_kvm=E2=80=99 77 | spr_register_kvm(env, num, name, uea_read, uea_write, = \ | ^~~~~~~~~~~~~~~~ ../../devel/qemu/target/ppc/cpu_init.c:894:9: note: in expansion of macro = =E2=80=98spr_register=E2=80=99 894 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", | ^~~~~~~~~~~~ ../../devel/qemu/target/ppc/cpu_init.c: In function =E2=80=98init_proc_e50= 0=E2=80=99: ../../devel/qemu/target/ppc/cpu_init.c:2809:14: note: at offset 12 into ob= ject =E2=80=98tlbncfg=E2=80=99 of size 8 2809 | uint32_t tlbncfg[2]; | ^~~~~~~ cc1: all warnings being treated as errors init_proc_e500() only defines "uint32_t tlbncfg[2];", but it is OK since it also sets "env->nb_ways =3D 2", so the code that GCC warns about in register_BookE206_sprs() is never reached. Unfortunately, GCC is not smart enough to see this, so it emits these warnings. To fix it, let's simplify the code in register_BookE206_sprs() a little bit to set up the SPRs in a loop, so we don't reference the tlbncfg[3] entry directly anymore. Signed-off-by: Thomas Huth Reviewed-by: Chinmay Rath --- target/ppc/cpu_init.c | 38 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3aa3aefc136..12c645699e8 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -850,6 +850,13 @@ static void register_BookE206_sprs(CPUPPCState *env, u= int32_t mas_mask, SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, }; + const char *tlbcfg_names[4] =3D { + "TLB0CFG", "TLB1CFG", "TLB2CFG", "TLB3CFG", + }; + const int tlbcfg_sprn[4] =3D { + SPR_BOOKE_TLB0CFG, SPR_BOOKE_TLB1CFG, + SPR_BOOKE_TLB2CFG, SPR_BOOKE_TLB3CFG, + }; int i; =20 /* TLB assist registers */ @@ -889,34 +896,13 @@ static void register_BookE206_sprs(CPUPPCState *env, = uint32_t mas_mask, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, mmucfg); - switch (env->nb_ways) { - case 4: - spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[3]); - /* Fallthru */ - case 3: - spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[2]); - /* Fallthru */ - case 2: - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[1]); - /* Fallthru */ - case 1: - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", + + assert(env->nb_ways <=3D ARRAY_SIZE(tlbcfg_names)); + for (i =3D 0; i < env->nb_ways; i++) { + spr_register(env, tlbcfg_sprn[i], tlbcfg_names[i], SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, - tlbncfg[0]); - /* Fallthru */ - case 0: - default: - break; + tlbncfg[i]); } #endif } --=20 2.51.0 From nobody Mon Oct 27 11:12:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=gaMiucdVxiolX0rROlrodd/rJ9B0e2SXKo+nqCeL5D/lF3vOqwxEc5GHfihbREwaQYLEf6 y8f7YGU5Hs2wMyDO4pg2QsDt7qzpVAeqlLpZIqHXbJuDOA6Z+/iw6XRXMP0q/0GZt2P05O jQiU3ZD7wVNVLvhrqqxNP5++ik8A3jw= X-MC-Unique: UcM_MFSuPmKxtAb0kmVsZA-1 X-Mimecast-MFC-AGG-ID: UcM_MFSuPmKxtAb0kmVsZA_1761289057 From: Thomas Huth To: Nicholas Piggin , Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 2/2] target/ppc: Remove the unusable e200 CPUs Date: Fri, 24 Oct 2025 08:57:26 +0200 Message-ID: <20251024065726.738005-3-thuth@redhat.com> In-Reply-To: <20251024065726.738005-1-thuth@redhat.com> References: <20251024065726.738005-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761289114477158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth There is currently no machine in QEMU (except the "none" machine) that can be run with with one of the e200 ppc CPUs - all machines either complain about an invalid CPU type or crash QEMU immediately. Looking at the history of this CPU type, it seems like it has never been used in QEMU and only implemented as a placeholder (see e.g. the comment about unimplemented instructions in the POWERPC_FAMILY(e200) section of cpu_init.c). Being completely unused and unusable since such a long time, let's just remove it now (without deprecation phase, since there were no users of this dead code anyway). Note: The init_excp_e200() is used by the e500 CPUs, too, so we rename this function to init_excp_e500() instead of removing it. Reviewed-by: Harsh Prateek Bora Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/cpu-models.h | 4 -- target/ppc/cpu-models.c | 5 -- target/ppc/cpu_init.c | 147 +--------------------------------------- 3 files changed, 2 insertions(+), 154 deletions(-) diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index c6cd27f390e..a439eb37ee4 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -120,10 +120,6 @@ enum { #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1 - /* e200 family */ - /* e200 cores */ - CPU_POWERPC_e200z5 =3D 0x81000000, - CPU_POWERPC_e200z6 =3D 0x81120000, /* e300 family */ /* e300 cores */ CPU_POWERPC_e300c1 =3D 0x00830010, diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 89ae763c7f6..26b6debcfc9 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -244,11 +244,6 @@ CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE) POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1", CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE) - /* e200 family = */ - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200, - "PowerPC e200z5 core") - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200, - "PowerPC e200z6 core") /* e300 family = */ POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300, "PowerPC e300c1 core") diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 12c645699e8..86ead740eec 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1811,7 +1811,7 @@ static void init_excp_G2(CPUPPCState *env) #endif } =20 -static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) +static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask) { #if !defined(CONFIG_USER_ONLY) env->excp_vectors[POWERPC_EXCP_RESET] =3D 0x00000FFC; @@ -2782,149 +2782,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *d= ata) POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; } =20 -static void init_proc_e200(CPUPPCState *env) -{ - register_BookE_sprs(env, 0x000000070000FFFFULL); - - spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", - &spr_read_spefscr, &spr_write_spefscr, - &spr_read_spefscr, &spr_write_spefscr, - 0x00000000); - /* Memory management */ - register_BookE206_sprs(env, 0x0000005D, NULL, 0); - register_usprgh_sprs(env); - - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_BUCSR, "BUCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_CTXCR, "CTXCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_DBCNT, "DBCNT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_DBCR3, "DBCR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - - spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); /* TOFIX */ - - init_tlbs_emb(env); - init_excp_e200(env, 0xFFFF0000UL); - env->dcache_line_size =3D 32; - env->icache_line_size =3D 32; - /* XXX: TODO: allocate internal IRQ controller */ -} - -POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - - dc->desc =3D "e200 core"; - pcc->init_proc =3D init_proc_e200; - pcc->check_pow =3D check_pow_hid0; - pcc->check_attn =3D check_attn_none; - /* - * XXX: unimplemented instructions: - * dcblc - * dcbtlst - * dcbtstls - * icblc - * icbtls - * tlbivax - * all SPE multiply-accumulate instructions - */ - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | - PPC_SPE | PPC_SPE_SINGLE | - PPC_WRTEE | PPC_RFDI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | - PPC_BOOKE; - pcc->msr_mask =3D (1ull << MSR_UCLE) | - (1ull << MSR_SPE) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model =3D POWERPC_MMU_BOOKE206; - pcc->excp_model =3D POWERPC_EXCP_BOOKE; - pcc->bus_model =3D PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach =3D bfd_mach_ppc_860; - pcc->flags =3D POWERPC_FLAG_SPE | POWERPC_FLAG_CE | - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - enum fsl_e500_version { fsl_e500v1, fsl_e500v2, @@ -3159,7 +3016,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) } #endif =20 - init_excp_e200(env, ivpr_mask); + init_excp_e500(env, ivpr_mask); /* Allocate hardware IRQ controller */ ppce500_irq_init(env_archcpu(env)); } --=20 2.51.0