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a="74137883" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137883" X-CSE-ConnectionGUID: k+loaOomT4esGWD24LR1Hg== X-CSE-MsgGUID: JXZ5mRxMRDa0NViqr9Tl8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276030" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 08/20] i386/cpu: Drop pmu check in CPUID 0x1C encoding Date: Fri, 24 Oct 2025 14:56:20 +0800 Message-Id: <20251024065632.1448606-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287774618158501 Content-Type: text/plain; charset="utf-8" Since CPUID_7_0_EDX_ARCH_LBR will be masked off if pmu is disabled, there's no need to check CPUID_7_0_EDX_ARCH_LBR feature with pmu. Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5b7a81fcdb1b..5cd335bb5574 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8275,11 +8275,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } break; } - case 0x1C: - if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { - x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); - *edx =3D 0; + case 0x1C: /* Last Branch Records Information Leaf */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { + break; } + x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); + *edx =3D 0; /* EDX is reserved. */ break; case 0x1D: { /* AMX TILE, for now hardcoded for Sapphire Rapids*/ --=20 2.34.1