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a="74137850" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137850" X-CSE-ConnectionGUID: zsC2s9jtQLe5bnxC3qm9UA== X-CSE-MsgGUID: rrYbULlzS9OvSizYjqVJPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184275869" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 01/20] linux-headers: Update to v6.18-rc2 Date: Fri, 24 Oct 2025 14:56:13 +0800 Message-Id: <20251024065632.1448606-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287766620158500 Content-Type: text/plain; charset="utf-8" Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- include/standard-headers/linux/ethtool.h | 1 + include/standard-headers/linux/fuse.h | 22 +- .../linux/input-event-codes.h | 1 + include/standard-headers/linux/input.h | 22 +- include/standard-headers/linux/pci_regs.h | 10 + include/standard-headers/linux/virtio_ids.h | 1 + include/standard-headers/linux/virtio_rtc.h | 237 ++++++++++++++++++ include/standard-headers/linux/virtio_spi.h | 181 +++++++++++++ linux-headers/asm-loongarch/kvm.h | 1 + linux-headers/asm-riscv/kvm.h | 23 +- linux-headers/asm-riscv/ptrace.h | 4 +- linux-headers/asm-x86/kvm.h | 34 +++ linux-headers/asm-x86/unistd_64.h | 1 + linux-headers/asm-x86/unistd_x32.h | 1 + linux-headers/linux/kvm.h | 3 + linux-headers/linux/psp-sev.h | 10 +- linux-headers/linux/stddef.h | 1 - linux-headers/linux/vduse.h | 2 +- linux-headers/linux/vhost.h | 4 +- 19 files changed, 548 insertions(+), 11 deletions(-) create mode 100644 include/standard-headers/linux/virtio_rtc.h create mode 100644 include/standard-headers/linux/virtio_spi.h diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-he= aders/linux/ethtool.h index eb803140283d..dc24512d2875 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -2380,6 +2380,7 @@ enum { #define RXH_L4_B_0_1 (1 << 6) /* src port in case of TCP/UDP/SCTP */ #define RXH_L4_B_2_3 (1 << 7) /* dst port in case of TCP/UDP/SCTP */ #define RXH_GTP_TEID (1 << 8) /* teid in case of GTP */ +#define RXH_IP6_FL (1 << 9) /* IPv6 flow label */ #define RXH_DISCARD (1 << 31) =20 #define RX_CLS_FLOW_DISC 0xffffffffffffffffULL diff --git a/include/standard-headers/linux/fuse.h b/include/standard-heade= rs/linux/fuse.h index d8b2fd67e16c..abf3a7885817 100644 --- a/include/standard-headers/linux/fuse.h +++ b/include/standard-headers/linux/fuse.h @@ -235,6 +235,11 @@ * * 7.44 * - add FUSE_NOTIFY_INC_EPOCH + * + * 7.45 + * - add FUSE_COPY_FILE_RANGE_64 + * - add struct fuse_copy_file_range_out + * - add FUSE_NOTIFY_PRUNE */ =20 #ifndef _LINUX_FUSE_H @@ -266,7 +271,7 @@ #define FUSE_KERNEL_VERSION 7 =20 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 44 +#define FUSE_KERNEL_MINOR_VERSION 45 =20 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -653,6 +658,7 @@ enum fuse_opcode { FUSE_SYNCFS =3D 50, FUSE_TMPFILE =3D 51, FUSE_STATX =3D 52, + FUSE_COPY_FILE_RANGE_64 =3D 53, =20 /* CUSE specific operations */ CUSE_INIT =3D 4096, @@ -671,7 +677,7 @@ enum fuse_notify_code { FUSE_NOTIFY_DELETE =3D 6, FUSE_NOTIFY_RESEND =3D 7, FUSE_NOTIFY_INC_EPOCH =3D 8, - FUSE_NOTIFY_CODE_MAX, + FUSE_NOTIFY_PRUNE =3D 9, }; =20 /* The read buffer is required to be at least 8k, but may be much larger */ @@ -1110,6 +1116,12 @@ struct fuse_notify_retrieve_in { uint64_t dummy4; }; =20 +struct fuse_notify_prune_out { + uint32_t count; + uint32_t padding; + uint64_t spare; +}; + struct fuse_backing_map { int32_t fd; uint32_t flags; @@ -1122,6 +1134,7 @@ struct fuse_backing_map { #define FUSE_DEV_IOC_BACKING_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 1, \ struct fuse_backing_map) #define FUSE_DEV_IOC_BACKING_CLOSE _IOW(FUSE_DEV_IOC_MAGIC, 2, uint32_t) +#define FUSE_DEV_IOC_SYNC_INIT _IO(FUSE_DEV_IOC_MAGIC, 3) =20 struct fuse_lseek_in { uint64_t fh; @@ -1144,6 +1157,11 @@ struct fuse_copy_file_range_in { uint64_t flags; }; =20 +/* For FUSE_COPY_FILE_RANGE_64 */ +struct fuse_copy_file_range_out { + uint64_t bytes_copied; +}; + #define FUSE_SETUPMAPPING_FLAG_WRITE (1ull << 0) #define FUSE_SETUPMAPPING_FLAG_READ (1ull << 1) struct fuse_setupmapping_in { diff --git a/include/standard-headers/linux/input-event-codes.h b/include/s= tandard-headers/linux/input-event-codes.h index 00dc9caac923..c914ccd7237a 100644 --- a/include/standard-headers/linux/input-event-codes.h +++ b/include/standard-headers/linux/input-event-codes.h @@ -27,6 +27,7 @@ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ +#define INPUT_PROP_HAPTIC_TOUCHPAD 0x07 /* is a haptic touchpad */ =20 #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) diff --git a/include/standard-headers/linux/input.h b/include/standard-head= ers/linux/input.h index d4512c20b543..9aff211dd561 100644 --- a/include/standard-headers/linux/input.h +++ b/include/standard-headers/linux/input.h @@ -426,6 +426,24 @@ struct ff_rumble_effect { uint16_t weak_magnitude; }; =20 +/** + * struct ff_haptic_effect + * @hid_usage: hid_usage according to Haptics page (WAVEFORM_CLICK, etc.) + * @vendor_id: the waveform vendor ID if hid_usage is in the vendor-define= d range + * @vendor_waveform_page: the vendor waveform page if hid_usage is in the = vendor-defined range + * @intensity: strength of the effect as percentage + * @repeat_count: number of times to retrigger effect + * @retrigger_period: time before effect is retriggered (in ms) + */ +struct ff_haptic_effect { + uint16_t hid_usage; + uint16_t vendor_id; + uint8_t vendor_waveform_page; + uint16_t intensity; + uint16_t repeat_count; + uint16_t retrigger_period; +}; + /** * struct ff_effect - defines force feedback effect * @type: type of the effect (FF_CONSTANT, FF_PERIODIC, FF_RAMP, FF_SPRING, @@ -462,6 +480,7 @@ struct ff_effect { struct ff_periodic_effect periodic; struct ff_condition_effect condition[2]; /* One for each axis */ struct ff_rumble_effect rumble; + struct ff_haptic_effect haptic; } u; }; =20 @@ -469,6 +488,7 @@ struct ff_effect { * Force feedback effect types */ =20 +#define FF_HAPTIC 0x4f #define FF_RUMBLE 0x50 #define FF_PERIODIC 0x51 #define FF_CONSTANT 0x52 @@ -478,7 +498,7 @@ struct ff_effect { #define FF_INERTIA 0x56 #define FF_RAMP 0x57 =20 -#define FF_EFFECT_MIN FF_RUMBLE +#define FF_EFFECT_MIN FF_HAPTIC #define FF_EFFECT_MAX FF_RAMP =20 /* diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-h= eaders/linux/pci_regs.h index f5b17745de60..07e06aafec50 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -207,6 +207,9 @@ =20 /* Capability lists */ =20 +#define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */ +#define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */ + #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ @@ -776,6 +779,12 @@ #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ +#define PCI_ERR_UNC_POISON_BLK 0x04000000 /* Poisoned TLP Egress Blocked = */ +#define PCI_ERR_UNC_DMWR_BLK 0x08000000 /* DMWr Request Egress Blocked */ +#define PCI_ERR_UNC_IDE_CHECK 0x10000000 /* IDE Check Failed */ +#define PCI_ERR_UNC_MISR_IDE 0x20000000 /* Misrouted IDE TLP */ +#define PCI_ERR_UNC_PCRC_CHECK 0x40000000 /* PCRC Check Failed */ +#define PCI_ERR_UNC_XLAT_BLK 0x80000000 /* TLP Translation Egress Blocked= */ #define PCI_ERR_UNCOR_MASK 0x08 /* Uncorrectable Error Mask */ /* Same bits as above */ #define PCI_ERR_UNCOR_SEVER 0x0c /* Uncorrectable Error Severity */ @@ -798,6 +807,7 @@ #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_CAP_PREFIX_LOG_PRESENT 0x00000800 /* TLP Prefix Log Prese= nt */ +#define PCI_ERR_CAP_COMP_TIME_LOG 0x00001000 /* Completion Timeout Prefix= /Header Log Capable */ #define PCI_ERR_CAP_TLP_LOG_FLIT 0x00040000 /* TLP was logged in Flit Mod= e */ #define PCI_ERR_CAP_TLP_LOG_SIZE 0x00f80000 /* Logged TLP Size (only in F= lit mode) */ #define PCI_ERR_HEADER_LOG 0x1c /* Header Log Register (16 bytes) */ diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard= -headers/linux/virtio_ids.h index 7aa2eb766205..6c12db16faa3 100644 --- a/include/standard-headers/linux/virtio_ids.h +++ b/include/standard-headers/linux/virtio_ids.h @@ -68,6 +68,7 @@ #define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ #define VIRTIO_ID_BT 40 /* virtio bluetooth */ #define VIRTIO_ID_GPIO 41 /* virtio gpio */ +#define VIRTIO_ID_SPI 45 /* virtio spi */ =20 /* * Virtio Transitional IDs diff --git a/include/standard-headers/linux/virtio_rtc.h b/include/standard= -headers/linux/virtio_rtc.h new file mode 100644 index 000000000000..7e2c21ebff58 --- /dev/null +++ b/include/standard-headers/linux/virtio_rtc.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-C= lause) */ +/* + * Copyright (C) 2022-2024 OpenSynergy GmbH + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _LINUX_VIRTIO_RTC_H +#define _LINUX_VIRTIO_RTC_H + +#include "standard-headers/linux/types.h" + +/* alarm feature */ +#define VIRTIO_RTC_F_ALARM 0 + +/* read request message types */ + +#define VIRTIO_RTC_REQ_READ 0x0001 +#define VIRTIO_RTC_REQ_READ_CROSS 0x0002 + +/* control request message types */ + +#define VIRTIO_RTC_REQ_CFG 0x1000 +#define VIRTIO_RTC_REQ_CLOCK_CAP 0x1001 +#define VIRTIO_RTC_REQ_CROSS_CAP 0x1002 +#define VIRTIO_RTC_REQ_READ_ALARM 0x1003 +#define VIRTIO_RTC_REQ_SET_ALARM 0x1004 +#define VIRTIO_RTC_REQ_SET_ALARM_ENABLED 0x1005 + +/* alarmq message types */ + +#define VIRTIO_RTC_NOTIF_ALARM 0x2000 + +/* Message headers */ + +/** common request header */ +struct virtio_rtc_req_head { + uint16_t msg_type; + uint8_t reserved[6]; +}; + +/** common response header */ +struct virtio_rtc_resp_head { +#define VIRTIO_RTC_S_OK 0 +#define VIRTIO_RTC_S_EOPNOTSUPP 2 +#define VIRTIO_RTC_S_ENODEV 3 +#define VIRTIO_RTC_S_EINVAL 4 +#define VIRTIO_RTC_S_EIO 5 + uint8_t status; + uint8_t reserved[7]; +}; + +/** common notification header */ +struct virtio_rtc_notif_head { + uint16_t msg_type; + uint8_t reserved[6]; +}; + +/* read requests */ + +/* VIRTIO_RTC_REQ_READ message */ + +struct virtio_rtc_req_read { + struct virtio_rtc_req_head head; + uint16_t clock_id; + uint8_t reserved[6]; +}; + +struct virtio_rtc_resp_read { + struct virtio_rtc_resp_head head; + uint64_t clock_reading; +}; + +/* VIRTIO_RTC_REQ_READ_CROSS message */ + +struct virtio_rtc_req_read_cross { + struct virtio_rtc_req_head head; + uint16_t clock_id; +/* Arm Generic Timer Counter-timer Virtual Count Register (CNTVCT_EL0) */ +#define VIRTIO_RTC_COUNTER_ARM_VCT 0 +/* x86 Time-Stamp Counter */ +#define VIRTIO_RTC_COUNTER_X86_TSC 1 +/* Invalid */ +#define VIRTIO_RTC_COUNTER_INVALID 0xFF + uint8_t hw_counter; + uint8_t reserved[5]; +}; + +struct virtio_rtc_resp_read_cross { + struct virtio_rtc_resp_head head; + uint64_t clock_reading; + uint64_t counter_cycles; +}; + +/* control requests */ + +/* VIRTIO_RTC_REQ_CFG message */ + +struct virtio_rtc_req_cfg { + struct virtio_rtc_req_head head; + /* no request params */ +}; + +struct virtio_rtc_resp_cfg { + struct virtio_rtc_resp_head head; + /** # of clocks -> clock ids < num_clocks are valid */ + uint16_t num_clocks; + uint8_t reserved[6]; +}; + +/* VIRTIO_RTC_REQ_CLOCK_CAP message */ + +struct virtio_rtc_req_clock_cap { + struct virtio_rtc_req_head head; + uint16_t clock_id; + uint8_t reserved[6]; +}; + +struct virtio_rtc_resp_clock_cap { + struct virtio_rtc_resp_head head; +#define VIRTIO_RTC_CLOCK_UTC 0 +#define VIRTIO_RTC_CLOCK_TAI 1 +#define VIRTIO_RTC_CLOCK_MONOTONIC 2 +#define VIRTIO_RTC_CLOCK_UTC_SMEARED 3 +#define VIRTIO_RTC_CLOCK_UTC_MAYBE_SMEARED 4 + uint8_t type; +#define VIRTIO_RTC_SMEAR_UNSPECIFIED 0 +#define VIRTIO_RTC_SMEAR_NOON_LINEAR 1 +#define VIRTIO_RTC_SMEAR_UTC_SLS 2 + uint8_t leap_second_smearing; +#define VIRTIO_RTC_FLAG_ALARM_CAP (1 << 0) + uint8_t flags; + uint8_t reserved[5]; +}; + +/* VIRTIO_RTC_REQ_CROSS_CAP message */ + +struct virtio_rtc_req_cross_cap { + struct virtio_rtc_req_head head; + uint16_t clock_id; + uint8_t hw_counter; + uint8_t reserved[5]; +}; + +struct virtio_rtc_resp_cross_cap { + struct virtio_rtc_resp_head head; +#define VIRTIO_RTC_FLAG_CROSS_CAP (1 << 0) + uint8_t flags; + uint8_t reserved[7]; +}; + +/* VIRTIO_RTC_REQ_READ_ALARM message */ + +struct virtio_rtc_req_read_alarm { + struct virtio_rtc_req_head head; + uint16_t clock_id; + uint8_t reserved[6]; +}; + +struct virtio_rtc_resp_read_alarm { + struct virtio_rtc_resp_head head; + uint64_t alarm_time; +#define VIRTIO_RTC_FLAG_ALARM_ENABLED (1 << 0) + uint8_t flags; + uint8_t reserved[7]; +}; + +/* VIRTIO_RTC_REQ_SET_ALARM message */ + +struct virtio_rtc_req_set_alarm { + struct virtio_rtc_req_head head; + uint64_t alarm_time; + uint16_t clock_id; + /* flag VIRTIO_RTC_FLAG_ALARM_ENABLED */ + uint8_t flags; + uint8_t reserved[5]; +}; + +struct virtio_rtc_resp_set_alarm { + struct virtio_rtc_resp_head head; + /* no response params */ +}; + +/* VIRTIO_RTC_REQ_SET_ALARM_ENABLED message */ + +struct virtio_rtc_req_set_alarm_enabled { + struct virtio_rtc_req_head head; + uint16_t clock_id; + /* flag VIRTIO_RTC_ALARM_ENABLED */ + uint8_t flags; + uint8_t reserved[5]; +}; + +struct virtio_rtc_resp_set_alarm_enabled { + struct virtio_rtc_resp_head head; + /* no response params */ +}; + +/** Union of request types for requestq */ +union virtio_rtc_req_requestq { + struct virtio_rtc_req_read read; + struct virtio_rtc_req_read_cross read_cross; + struct virtio_rtc_req_cfg cfg; + struct virtio_rtc_req_clock_cap clock_cap; + struct virtio_rtc_req_cross_cap cross_cap; + struct virtio_rtc_req_read_alarm read_alarm; + struct virtio_rtc_req_set_alarm set_alarm; + struct virtio_rtc_req_set_alarm_enabled set_alarm_enabled; +}; + +/** Union of response types for requestq */ +union virtio_rtc_resp_requestq { + struct virtio_rtc_resp_read read; + struct virtio_rtc_resp_read_cross read_cross; + struct virtio_rtc_resp_cfg cfg; + struct virtio_rtc_resp_clock_cap clock_cap; + struct virtio_rtc_resp_cross_cap cross_cap; + struct virtio_rtc_resp_read_alarm read_alarm; + struct virtio_rtc_resp_set_alarm set_alarm; + struct virtio_rtc_resp_set_alarm_enabled set_alarm_enabled; +}; + +/* alarmq notifications */ + +/* VIRTIO_RTC_NOTIF_ALARM notification */ + +struct virtio_rtc_notif_alarm { + struct virtio_rtc_notif_head head; + uint16_t clock_id; + uint8_t reserved[6]; +}; + +/** Union of notification types for alarmq */ +union virtio_rtc_notif_alarmq { + struct virtio_rtc_notif_alarm alarm; +}; + +#endif /* _LINUX_VIRTIO_RTC_H */ diff --git a/include/standard-headers/linux/virtio_spi.h b/include/standard= -headers/linux/virtio_spi.h new file mode 100644 index 000000000000..54e570fb4a84 --- /dev/null +++ b/include/standard-headers/linux/virtio_spi.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2023 OpenSynergy GmbH + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H +#define _LINUX_VIRTIO_VIRTIO_SPI_H + +#include "standard-headers/linux/types.h" +#include "standard-headers/linux/virtio_config.h" +#include "standard-headers/linux/virtio_ids.h" +#include "standard-headers/linux/virtio_types.h" + +/* Sample data on trailing clock edge */ +#define VIRTIO_SPI_CPHA _BITUL(0) +/* Clock is high when IDLE */ +#define VIRTIO_SPI_CPOL _BITUL(1) +/* Chip Select is active high */ +#define VIRTIO_SPI_CS_HIGH _BITUL(2) +/* Transmit LSB first */ +#define VIRTIO_SPI_MODE_LSB_FIRST _BITUL(3) +/* Loopback mode */ +#define VIRTIO_SPI_MODE_LOOP _BITUL(4) + +/** + * struct virtio_spi_config - All config fields are read-only for the + * Virtio SPI driver + * @cs_max_number: maximum number of chipselect the host SPI controller + * supports. + * @cs_change_supported: indicates if the host SPI controller supports to = toggle + * chipselect after each transfer in one message: + * 0: unsupported, chipselect will be kept in active state throughout the + * message transaction; + * 1: supported. + * Note: Message here contains a sequence of SPI transfers. + * @tx_nbits_supported: indicates the supported number of bit for writing: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @rx_nbits_supported: indicates the supported number of bit for reading: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @bits_per_word_mask: mask indicating which values of bits_per_word are + * supported. If not set, no limitation for bits_per_word. + * @mode_func_supported: indicates the following features are supported or= not: + * bit 0-1: CPHA feature + * 0b00: invalid, should support as least one CPHA setting + * 0b01: supports CPHA=3D0 only + * 0b10: supports CPHA=3D1 only + * 0b11: supports CPHA=3D0 and CPHA=3D1. + * bit 2-3: CPOL feature + * 0b00: invalid, should support as least one CPOL setting + * 0b01: supports CPOL=3D0 only + * 0b10: supports CPOL=3D1 only + * 0b11: supports CPOL=3D0 and CPOL=3D1. + * bit 4: chipselect active high feature, 0 for unsupported and 1 for + * supported, chipselect active low is supported by default. + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, + * MSB first is supported by default. + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, + * normal mode is supported by default. + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no + * limitation for transfer speed. + * @max_word_delay_ns: the maximum word delay supported, in nanoseconds. + * A value of 0 indicates that word delay is unsupported. + * Each transfer may consist of a sequence of words. + * @max_cs_setup_ns: the maximum delay supported after chipselect is asser= ted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * asserted. + * @max_cs_hold_ns: the maximum delay supported before chipselect is deass= erted, + * in ns unit, 0 means delay is not supported to introduce before chipse= lect + * is deasserted. + * @max_cs_incative_ns: maximum delay supported after chipselect is deasse= rted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * deasserted. + */ +struct virtio_spi_config { + uint8_t cs_max_number; + uint8_t cs_change_supported; +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL _BITUL(0) +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD _BITUL(1) +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL _BITUL(2) + uint8_t tx_nbits_supported; + uint8_t rx_nbits_supported; + uint32_t bits_per_word_mask; +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 _BITUL(0) +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 _BITUL(1) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 _BITUL(2) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 _BITUL(3) +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH _BITUL(4) +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST _BITUL(5) +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK _BITUL(6) + uint32_t mode_func_supported; + uint32_t max_freq_hz; + uint32_t max_word_delay_ns; + uint32_t max_cs_setup_ns; + uint32_t max_cs_hold_ns; + uint32_t max_cs_inactive_ns; +}; + +/** + * struct spi_transfer_head - virtio SPI transfer descriptor + * @chip_select_id: chipselect index the SPI transfer used. + * @bits_per_word: the number of bits in each SPI transfer word. + * @cs_change: whether to deselect device after finishing this transfer + * before starting the next transfer, 0 means cs keep asserted and + * 1 means cs deasserted then asserted again. + * @tx_nbits: bus width for write transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * @rx_nbits: bus width for read transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * @reserved: for future use. + * @mode: SPI transfer mode. + * bit 0: CPHA, determines the timing (i.e. phase) of the data + * bits relative to the clock pulses.For CPHA=3D0, the + * "out" side changes the data on the trailing edge of the + * preceding clock cycle, while the "in" side captures the data + * on (or shortly after) the leading edge of the clock cycle. + * For CPHA=3D1, the "out" side changes the data on the leading + * edge of the current clock cycle, while the "in" side + * captures the data on (or shortly after) the trailing edge of + * the clock cycle. + * bit 1: CPOL, determines the polarity of the clock. CPOL=3D0 is a + * clock which idles at 0, and each cycle consists of a pulse + * of 1. CPOL=3D1 is a clock which idles at 1, and each cycle + * consists of a pulse of 0. + * bit 2: CS_HIGH, if 1, chip select active high, else active low. + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB + * first, else LSB first. + * bit 4: LOOP, loopback mode. + * @freq: the transfer speed in Hz. + * @word_delay_ns: delay to be inserted between consecutive words of a + * transfer, in ns unit. + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns + * unit. + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted + * for each transfer, in ns unit. + * @cs_change_delay_inactive_ns: delay to be introduced after CS is + * deasserted and before next asserted, in ns unit. + */ +struct spi_transfer_head { + uint8_t chip_select_id; + uint8_t bits_per_word; + uint8_t cs_change; + uint8_t tx_nbits; + uint8_t rx_nbits; + uint8_t reserved[3]; + uint32_t mode; + uint32_t freq; + uint32_t word_delay_ns; + uint32_t cs_setup_ns; + uint32_t cs_delay_hold_ns; + uint32_t cs_change_delay_inactive_ns; +}; + +/** + * struct spi_transfer_result - virtio SPI transfer result + * @result: Transfer result code. + * VIRTIO_SPI_TRANS_OK: Transfer successful. + * VIRTIO_SPI_PARAM_ERR: Parameter error. + * VIRTIO_SPI_TRANS_ERR: Transfer error. + */ +struct spi_transfer_result { +#define VIRTIO_SPI_TRANS_OK 0 +#define VIRTIO_SPI_PARAM_ERR 1 +#define VIRTIO_SPI_TRANS_ERR 2 + uint8_t result; +}; + +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */ diff --git a/linux-headers/asm-loongarch/kvm.h b/linux-headers/asm-loongarc= h/kvm.h index 5f354f5c6847..57ba1a563bb1 100644 --- a/linux-headers/asm-loongarch/kvm.h +++ b/linux-headers/asm-loongarch/kvm.h @@ -103,6 +103,7 @@ struct kvm_fpu { #define KVM_LOONGARCH_VM_FEAT_PMU 5 #define KVM_LOONGARCH_VM_FEAT_PV_IPI 6 #define KVM_LOONGARCH_VM_FEAT_PV_STEALTIME 7 +#define KVM_LOONGARCH_VM_FEAT_PTW 8 =20 /* Device Control API on vcpu fd */ #define KVM_LOONGARCH_VCPU_CPUCFG 0 diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h index ef27d4289da1..759a4852c09a 100644 --- a/linux-headers/asm-riscv/kvm.h +++ b/linux-headers/asm-riscv/kvm.h @@ -9,7 +9,7 @@ #ifndef __LINUX_KVM_RISCV_H #define __LINUX_KVM_RISCV_H =20 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ =20 #include #include @@ -56,6 +56,7 @@ struct kvm_riscv_config { unsigned long mimpid; unsigned long zicboz_block_size; unsigned long satp_mode; + unsigned long zicbop_block_size; }; =20 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ @@ -185,6 +186,10 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZICCRSE, KVM_RISCV_ISA_EXT_ZAAMO, KVM_RISCV_ISA_EXT_ZALRSC, + KVM_RISCV_ISA_EXT_ZICBOP, + KVM_RISCV_ISA_EXT_ZFBFMIN, + KVM_RISCV_ISA_EXT_ZVFBFMIN, + KVM_RISCV_ISA_EXT_ZVFBFWMA, KVM_RISCV_ISA_EXT_MAX, }; =20 @@ -205,6 +210,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_STA, KVM_RISCV_SBI_EXT_SUSP, + KVM_RISCV_SBI_EXT_FWFT, KVM_RISCV_SBI_EXT_MAX, }; =20 @@ -214,6 +220,18 @@ struct kvm_riscv_sbi_sta { unsigned long shmem_hi; }; =20 +struct kvm_riscv_sbi_fwft_feature { + unsigned long enable; + unsigned long flags; + unsigned long value; +}; + +/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sbi_fwft { + struct kvm_riscv_sbi_fwft_feature misaligned_deleg; + struct kvm_riscv_sbi_fwft_feature pointer_masking; +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -297,6 +315,9 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_SBI_STA_REG(name) \ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_FWFT_REG(name) \ + (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) =20 /* Device Control API: RISC-V AIA */ #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 diff --git a/linux-headers/asm-riscv/ptrace.h b/linux-headers/asm-riscv/ptr= ace.h index 1e3166caca8c..a3f8211ede44 100644 --- a/linux-headers/asm-riscv/ptrace.h +++ b/linux-headers/asm-riscv/ptrace.h @@ -6,7 +6,7 @@ #ifndef _ASM_RISCV_PTRACE_H #define _ASM_RISCV_PTRACE_H =20 -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ =20 #include =20 @@ -127,6 +127,6 @@ struct __riscv_v_regset_state { */ #define RISCV_MAX_VLENB (8192) =20 -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ =20 #endif /* _ASM_RISCV_PTRACE_H */ diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index f0c1a730d9c3..3bb38f6c3a41 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -35,6 +35,11 @@ #define MC_VECTOR 18 #define XM_VECTOR 19 #define VE_VECTOR 20 +#define CP_VECTOR 21 + +#define HV_VECTOR 28 +#define VC_VECTOR 29 +#define SX_VECTOR 30 =20 /* Select x86 specific features in */ #define __KVM_HAVE_PIT @@ -409,6 +414,35 @@ struct kvm_xcrs { __u64 padding[16]; }; =20 +#define KVM_X86_REG_TYPE_MSR 2 +#define KVM_X86_REG_TYPE_KVM 3 + +#define KVM_X86_KVM_REG_SIZE(reg) \ +({ \ + reg =3D=3D KVM_REG_GUEST_SSP ? KVM_REG_SIZE_U64 : 0; \ +}) + +#define KVM_X86_REG_TYPE_SIZE(type, reg) \ +({ \ + __u64 type_size =3D (__u64)type << 32; \ + \ + type_size |=3D type =3D=3D KVM_X86_REG_TYPE_MSR ? KVM_REG_SIZE_U64 : \ + type =3D=3D KVM_X86_REG_TYPE_KVM ? KVM_X86_KVM_REG_SIZE(reg) : \ + 0; \ + type_size; \ +}) + +#define KVM_X86_REG_ID(type, index) \ + (KVM_REG_X86 | KVM_X86_REG_TYPE_SIZE(type, index) | index) + +#define KVM_X86_REG_MSR(index) \ + KVM_X86_REG_ID(KVM_X86_REG_TYPE_MSR, index) +#define KVM_X86_REG_KVM(index) \ + KVM_X86_REG_ID(KVM_X86_REG_TYPE_KVM, index) + +/* KVM-defined registers starting from 0 */ +#define KVM_REG_GUEST_SSP 0 + #define KVM_SYNC_X86_REGS (1UL << 0) #define KVM_SYNC_X86_SREGS (1UL << 1) #define KVM_SYNC_X86_EVENTS (1UL << 2) diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unis= td_64.h index 2f55bebb81cc..26c258d1a609 100644 --- a/linux-headers/asm-x86/unistd_64.h +++ b/linux-headers/asm-x86/unistd_64.h @@ -337,6 +337,7 @@ #define __NR_io_pgetevents 333 #define __NR_rseq 334 #define __NR_uretprobe 335 +#define __NR_uprobe 336 #define __NR_pidfd_send_signal 424 #define __NR_io_uring_setup 425 #define __NR_io_uring_enter 426 diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/uni= std_x32.h index 8cc8673f1547..65c2aed94623 100644 --- a/linux-headers/asm-x86/unistd_x32.h +++ b/linux-headers/asm-x86/unistd_x32.h @@ -290,6 +290,7 @@ #define __NR_io_pgetevents (__X32_SYSCALL_BIT + 333) #define __NR_rseq (__X32_SYSCALL_BIT + 334) #define __NR_uretprobe (__X32_SYSCALL_BIT + 335) +#define __NR_uprobe (__X32_SYSCALL_BIT + 336) #define __NR_pidfd_send_signal (__X32_SYSCALL_BIT + 424) #define __NR_io_uring_setup (__X32_SYSCALL_BIT + 425) #define __NR_io_uring_enter (__X32_SYSCALL_BIT + 426) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index be704965d865..4ea28ef7cac1 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -954,6 +954,7 @@ struct kvm_enable_cap { #define KVM_CAP_ARM_EL2_E2H0 241 #define KVM_CAP_RISCV_MP_STATE_RESET 242 #define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 243 +#define KVM_CAP_GUEST_MEMFD_FLAGS 244 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; @@ -1590,6 +1591,8 @@ struct kvm_memory_attributes { #define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3) =20 #define KVM_CREATE_GUEST_MEMFD _IOWR(KVMIO, 0xd4, struct kvm_create_guest= _memfd) +#define GUEST_MEMFD_FLAG_MMAP (1ULL << 0) +#define GUEST_MEMFD_FLAG_INIT_SHARED (1ULL << 1) =20 struct kvm_create_guest_memfd { __u64 size; diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h index 113c4ceb7840..c525125ea815 100644 --- a/linux-headers/linux/psp-sev.h +++ b/linux-headers/linux/psp-sev.h @@ -185,6 +185,10 @@ struct sev_user_data_get_id2 { * @mask_chip_id: whether chip id is present in attestation reports or not * @mask_chip_key: whether attestation reports are signed or not * @vlek_en: VLEK (Version Loaded Endorsement Key) hashstick is loaded + * @feature_info: whether SNP_FEATURE_INFO command is available + * @rapl_dis: whether RAPL is disabled + * @ciphertext_hiding_cap: whether platform has ciphertext hiding capabili= ty + * @ciphertext_hiding_en: whether ciphertext hiding is enabled * @rsvd1: reserved * @guest_count: the number of guest currently managed by the firmware * @current_tcb_version: current TCB version @@ -200,7 +204,11 @@ struct sev_user_data_snp_status { __u32 mask_chip_id:1; /* Out */ __u32 mask_chip_key:1; /* Out */ __u32 vlek_en:1; /* Out */ - __u32 rsvd1:29; + __u32 feature_info:1; /* Out */ + __u32 rapl_dis:1; /* Out */ + __u32 ciphertext_hiding_cap:1; /* Out */ + __u32 ciphertext_hiding_en:1; /* Out */ + __u32 rsvd1:25; __u32 guest_count; /* Out */ __u64 current_tcb_version; /* Out */ __u64 reported_tcb_version; /* Out */ diff --git a/linux-headers/linux/stddef.h b/linux-headers/linux/stddef.h index e1fcfcf3b332..48ee4438e0ef 100644 --- a/linux-headers/linux/stddef.h +++ b/linux-headers/linux/stddef.h @@ -3,7 +3,6 @@ #define _LINUX_STDDEF_H =20 =20 - #ifndef __always_inline #define __always_inline __inline__ #endif diff --git a/linux-headers/linux/vduse.h b/linux-headers/linux/vduse.h index f46269af349a..da6ac89af18e 100644 --- a/linux-headers/linux/vduse.h +++ b/linux-headers/linux/vduse.h @@ -237,7 +237,7 @@ struct vduse_iova_umem { * struct vduse_iova_info - information of one IOVA region * @start: start of the IOVA region * @last: last of the IOVA region - * @capability: capability of the IOVA regsion + * @capability: capability of the IOVA region * @reserved: for future use, needs to be initialized to zero * * Structure used by VDUSE_IOTLB_GET_INFO ioctl to get information of diff --git a/linux-headers/linux/vhost.h b/linux-headers/linux/vhost.h index 283348b64af9..c57674a6aa0d 100644 --- a/linux-headers/linux/vhost.h +++ b/linux-headers/linux/vhost.h @@ -260,7 +260,7 @@ * When fork_owner is set to VHOST_FORK_OWNER_KTHREAD: * - Vhost will create vhost workers as kernel threads. */ -#define VHOST_SET_FORK_FROM_OWNER _IOW(VHOST_VIRTIO, 0x83, __u8) +#define VHOST_SET_FORK_FROM_OWNER _IOW(VHOST_VIRTIO, 0x84, __u8) =20 /** * VHOST_GET_FORK_OWNER - Get the current fork_owner flag for the vhost de= vice. @@ -268,6 +268,6 @@ * * @return: An 8-bit value indicating the current thread mode. */ -#define VHOST_GET_FORK_FROM_OWNER _IOR(VHOST_VIRTIO, 0x84, __u8) +#define VHOST_GET_FORK_FROM_OWNER _IOR(VHOST_VIRTIO, 0x85, __u8) =20 #endif --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="74137853" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137853" X-CSE-ConnectionGUID: 0QUAmH1gS9qrgLL/Dkmxkw== X-CSE-MsgGUID: wy5mimrYRdKnHSHnHgvAzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184275882" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 02/20] i386/cpu: Clean up indent style of x86_ext_save_areas[] Date: Fri, 24 Oct 2025 14:56:14 +0800 Message-Id: <20251024065632.1448606-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287764537158500 Content-Type: text/plain; charset="utf-8" Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- target/i386/cpu.c | 58 +++++++++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0a66e1fec939..f0e179c2d235 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2028,38 +2028,46 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COU= NT] =3D { .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_XSAVE, .size =3D sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), }, - [XSTATE_YMM_BIT] =3D - { .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_AVX, - .size =3D sizeof(XSaveAVX) }, - [XSTATE_BNDREGS_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .size =3D sizeof(XSaveBNDREG) }, - [XSTATE_BNDCSR_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .size =3D sizeof(XSaveBNDCSR) }, - [XSTATE_OPMASK_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveOpmask) }, - [XSTATE_ZMM_Hi256_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveZMM_Hi256) }, - [XSTATE_Hi16_ZMM_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveHi16_ZMM) }, - [XSTATE_PKRU_BIT] =3D - { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, - .size =3D sizeof(XSavePKRU) }, + [XSTATE_YMM_BIT] =3D { + .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_AVX, + .size =3D sizeof(XSaveAVX), + }, + [XSTATE_BNDREGS_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, + .size =3D sizeof(XSaveBNDREG), + }, + [XSTATE_BNDCSR_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, + .size =3D sizeof(XSaveBNDCSR), + }, + [XSTATE_OPMASK_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveOpmask), + }, + [XSTATE_ZMM_Hi256_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveZMM_Hi256), + }, + [XSTATE_Hi16_ZMM_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveHi16_ZMM), + }, + [XSTATE_PKRU_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, + .size =3D sizeof(XSavePKRU), + }, [XSTATE_ARCH_LBR_BIT] =3D { - .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, - .offset =3D 0 /*supervisor mode component, offset =3D 0 */, - .size =3D sizeof(XSavesArchLBR) }, + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, + .offset =3D 0 /*supervisor mode component, offset =3D 0 */, + .size =3D sizeof(XSavesArchLBR), + }, [XSTATE_XTILE_CFG_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, .size =3D sizeof(XSaveXTILECFG), }, [XSTATE_XTILE_DATA_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, - .size =3D sizeof(XSaveXTILEDATA) + .size =3D sizeof(XSaveXTILEDATA), }, }; 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a="74137856" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137856" X-CSE-ConnectionGUID: iSPyFyu9TS+/duopMWN8EA== X-CSE-MsgGUID: UFkaiXBHQoesSMsDwixM+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184275896" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 03/20] i386/cpu: Clean up arch lbr xsave struct and comment Date: Fri, 24 Oct 2025 14:56:15 +0800 Message-Id: <20251024065632.1448606-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287754549158500 Content-Type: text/plain; charset="utf-8" Arch LBR state is area 15, not 19. Fix this comment. And considerring other areas don't mention user or supervisor state, for consistent style, remove "Supervisor mode" from its comment. Moreover, rename XSavesArchLBR to XSaveArchLBR since there's no need to emphasize XSAVES in naming; the XSAVE related structure is mainly used to represent memory layout. In addition, arch lbr specifies its offset of xsave component as 0. But this cannot help on anything. The offset of ExtSaveArea is initialized by accelerators (e.g., hvf_cpu_xsave_init(), kvm_cpu_xsave_init() and x86_tcg_cpu_xsave_init()), so explicitly setting the offset doesn't work and CPUID 0xD encoding has already ensure supervisor states won't have non-zero offsets. Drop the offset initialization and its comment from the xsave area of arch lbr. Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/cpu.c | 3 +-- target/i386/cpu.h | 8 ++++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f0e179c2d235..b9a5a0400dea 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2058,8 +2058,7 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT= ] =3D { }, [XSTATE_ARCH_LBR_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, - .offset =3D 0 /*supervisor mode component, offset =3D 0 */, - .size =3D sizeof(XSavesArchLBR), + .size =3D sizeof(XSaveArchLBR), }, [XSTATE_XTILE_CFG_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d0da9bfe58ce..886a941e481c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1747,15 +1747,15 @@ typedef struct { =20 #define ARCH_LBR_NR_ENTRIES 32 =20 -/* Ext. save area 19: Supervisor mode Arch LBR state */ -typedef struct XSavesArchLBR { +/* Ext. save area 15: Arch LBR state */ +typedef struct XSaveArchLBR { uint64_t lbr_ctl; uint64_t lbr_depth; uint64_t ler_from; uint64_t ler_to; uint64_t ler_info; LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; -} XSavesArchLBR; +} XSaveArchLBR; =20 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); @@ -1766,7 +1766,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); -QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) !=3D 0x328); +QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); =20 typedef struct ExtSaveArea { uint32_t feature, bits; --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="184275918" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 04/20] i386/cpu: Reorganize arch lbr structure definitions Date: Fri, 24 Oct 2025 14:56:16 +0800 Message-Id: <20251024065632.1448606-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287754590158500 Content-Type: text/plain; charset="utf-8" - Move ARCH_LBR_NR_ENTRIES macro and LBREntry definition before XSAVE areas definitions. - Reorder XSavesArchLBR (area 15) between XSavePKRU (area 9) and XSaveXTILECFG (area 17), and reorder the related QEMU_BUILD_BUG_ON check to keep the same ordering. This makes xsave structures to be organized together and makes them clearer. Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/cpu.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 886a941e481c..ac527971d8cd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1652,6 +1652,14 @@ typedef struct { =20 #define NB_OPMASK_REGS 8 =20 +typedef struct { + uint64_t from; + uint64_t to; + uint64_t info; +} LBREntry; + +#define ARCH_LBR_NR_ENTRIES 32 + /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish * that APIC ID hasn't been set yet */ @@ -1729,24 +1737,6 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 -/* Ext. save area 17: AMX XTILECFG state */ -typedef struct XSaveXTILECFG { - uint8_t xtilecfg[64]; -} XSaveXTILECFG; - -/* Ext. save area 18: AMX XTILEDATA state */ -typedef struct XSaveXTILEDATA { - uint8_t xtiledata[8][1024]; -} XSaveXTILEDATA; - -typedef struct { - uint64_t from; - uint64_t to; - uint64_t info; -} LBREntry; - -#define ARCH_LBR_NR_ENTRIES 32 - /* Ext. save area 15: Arch LBR state */ typedef struct XSaveArchLBR { uint64_t lbr_ctl; @@ -1757,6 +1747,16 @@ typedef struct XSaveArchLBR { LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; } XSaveArchLBR; =20 +/* Ext. save area 17: AMX XTILECFG state */ +typedef struct XSaveXTILECFG { + uint8_t xtilecfg[64]; +} XSaveXTILECFG; + +/* Ext. save area 18: AMX XTILEDATA state */ +typedef struct XSaveXTILEDATA { + uint8_t xtiledata[8][1024]; +} XSaveXTILEDATA; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1764,9 +1764,9 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); -QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); =20 typedef struct ExtSaveArea { uint32_t feature, bits; --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287750; cv=none; d=zohomail.com; s=zohoarc; b=d/oIkS4n6oFsO9B2pd6Y/ECFGgF0J9vdeNPy8pee3Fy0Uo7VZ2VtKEWKjqS++D6zTR6bw1BOz6zIL6cmPhNomZJ7TmZszVbYDCK12PrAFxR16EpA9OpC2VEMcNUaWiPiiMW9NN2oHIV53SSbEtsoSs4YBzB/7YyDC6mg5BpQ5cA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761287750; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: RQHDUqqKQlGKBph6DDgOTA== X-CSE-MsgGUID: lLktCpLWRk2qKJvAERcPHg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="74137872" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137872" X-CSE-ConnectionGUID: OTV5HSueQcegg7LYrw+/3Q== X-CSE-MsgGUID: G++/779WSp2AQWxCYxEhPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184275927" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 05/20] i386/cpu: Make ExtSaveArea store an array of dependencies Date: Fri, 24 Oct 2025 14:56:17 +0800 Message-Id: <20251024065632.1448606-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287754640158500 Content-Type: text/plain; charset="utf-8" Some XSAVE components depend on multiple features. For example, Opmask/ ZMM_Hi256/Hi16_ZMM depend on avx512f OR avx10, and for CET (which will be supported later), cet_u/cet_s will depend on shstk OR ibt. Although previously there's the special check for the dependencies of AVX512F OR AVX10 on their respective XSAVE components (in cpuid_has_xsave_feature()), to make the code more general and avoid adding more special cases, make ExtSaveArea store a features array instead of a single feature, so that it can describe multiple dependencies. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.c | 71 ++++++++++++++++++++++++++++++++++------------- target/i386/cpu.h | 9 +++++- 2 files changed, 59 insertions(+), 21 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b9a5a0400dea..cd269d15ce0b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2020,53 +2020,77 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_= NB_REGS32] =3D { ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] =3D { [XSTATE_FP_BIT] =3D { /* x87 FP state component is always enabled if XSAVE is supported = */ - .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_XSAVE, .size =3D sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), + .features =3D { + { FEAT_1_ECX, CPUID_EXT_XSAVE }, + }, }, [XSTATE_SSE_BIT] =3D { /* SSE state component is always enabled if XSAVE is supported */ - .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_XSAVE, .size =3D sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), + .features =3D { + { FEAT_1_ECX, CPUID_EXT_XSAVE }, + }, }, [XSTATE_YMM_BIT] =3D { - .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_AVX, .size =3D sizeof(XSaveAVX), + .features =3D { + { FEAT_1_ECX, CPUID_EXT_AVX }, + }, }, [XSTATE_BNDREGS_BIT] =3D { - .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, .size =3D sizeof(XSaveBNDREG), + .features =3D { + { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, + }, }, [XSTATE_BNDCSR_BIT] =3D { - .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, .size =3D sizeof(XSaveBNDCSR), + .features =3D { + { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, + }, }, [XSTATE_OPMASK_BIT] =3D { - .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, .size =3D sizeof(XSaveOpmask), + .features =3D { + { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + }, }, [XSTATE_ZMM_Hi256_BIT] =3D { - .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, .size =3D sizeof(XSaveZMM_Hi256), + .features =3D { + { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + }, }, [XSTATE_Hi16_ZMM_BIT] =3D { - .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, .size =3D sizeof(XSaveHi16_ZMM), + .features =3D { + { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + }, }, [XSTATE_PKRU_BIT] =3D { - .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .size =3D sizeof(XSavePKRU), + .features =3D { + { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU }, + }, }, [XSTATE_ARCH_LBR_BIT] =3D { - .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, .size =3D sizeof(XSaveArchLBR), + .features =3D { + { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_LBR }, + }, }, [XSTATE_XTILE_CFG_BIT] =3D { - .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, .size =3D sizeof(XSaveXTILECFG), + .features =3D { + { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + }, }, [XSTATE_XTILE_DATA_BIT] =3D { - .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, .size =3D sizeof(XSaveXTILEDATA), + .features =3D { + { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + }, }, }; =20 @@ -7137,10 +7161,13 @@ static const char *x86_cpu_feature_name(FeatureWord= w, int bitnr) if (w =3D=3D FEAT_XSAVE_XCR0_LO || w =3D=3D FEAT_XSAVE_XCR0_HI) { int comp =3D (w =3D=3D FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; =20 - if (comp < ARRAY_SIZE(x86_ext_save_areas) && - x86_ext_save_areas[comp].bits) { - w =3D x86_ext_save_areas[comp].feature; - bitnr =3D ctz32(x86_ext_save_areas[comp].bits); + if (comp < ARRAY_SIZE(x86_ext_save_areas)) { + /* Present the first feature as the default. */ + const FeatureMask *fm =3D &x86_ext_save_areas[comp].features[0= ]; + if (fm->mask !=3D 0) { + w =3D fm->index; + bitnr =3D ctz32(fm->mask); + } } } =20 @@ -8610,11 +8637,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *en= v, const ExtSaveArea *esa) return false; } =20 - if (env->features[esa->feature] & esa->bits) { - return true; + for (int i =3D 0; i < ARRAY_SIZE(esa->features); i++) { + if (env->features[esa->features[i].index] & esa->features[i].mask)= { + return true; + } } - if (esa->feature =3D=3D FEAT_7_0_EBX && esa->bits =3D=3D CPUID_7_0_EBX= _AVX512F - && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + + if (esa->features[0].index =3D=3D FEAT_7_0_EBX && + esa->features[0].mask =3D=3D CPUID_7_0_EBX_AVX512F && + (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { return true; } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ac527971d8cd..6537affcf067 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1769,9 +1769,16 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); =20 typedef struct ExtSaveArea { - uint32_t feature, bits; uint32_t offset, size; uint32_t ecx; + /* + * The dependencies in the array work as OR relationships, which + * means having just one of those features is enough. + * + * At most two features are sharing the same xsave area. + * Number of features can be adjusted if necessary. + */ + const FeatureMask features[2]; } ExtSaveArea; =20 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="184275952" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 06/20] i386/cpu: Add avx10 dependency for Opmask/ZMM_Hi256/Hi16_ZMM Date: Fri, 24 Oct 2025 14:56:18 +0800 Message-Id: <20251024065632.1448606-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287768471158500 Content-Type: text/plain; charset="utf-8" With feature array in ExtSaveArea, add avx10 as the second dependency for Opmask/ZMM_Hi256/Hi16_ZMM xsave components, and drop the special check in cpuid_has_xsave_feature(). Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- target/i386/cpu.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cd269d15ce0b..236a2f3a9426 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2054,18 +2054,21 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COU= NT] =3D { .size =3D sizeof(XSaveOpmask), .features =3D { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_ZMM_Hi256_BIT] =3D { .size =3D sizeof(XSaveZMM_Hi256), .features =3D { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_Hi16_ZMM_BIT] =3D { .size =3D sizeof(XSaveHi16_ZMM), .features =3D { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_PKRU_BIT] =3D { @@ -8643,12 +8646,6 @@ static bool cpuid_has_xsave_feature(CPUX86State *env= , const ExtSaveArea *esa) } } =20 - if (esa->features[0].index =3D=3D FEAT_7_0_EBX && - esa->features[0].mask =3D=3D CPUID_7_0_EBX_AVX512F && - (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { - return true; 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Fri, 24 Oct 2025 02:35:08 -0400 Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 23:35:06 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa006.fm.intel.com with ESMTP; 23 Oct 2025 23:35:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761287707; x=1792823707; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QsEIvetAm56gQ1P0v2fnMFkaIiEYaCzYU/UNfr2qDKQ=; b=Xm/3G37yqQjvztD90NXwJMVLclbw3sbWFc56BI91Ig7KPhxssrOtAfBt jPko0+XMZ2Xp7rrCxUhvDrXrWGXBR4154bNxjxtE4gqwjug8b9eLh/sEq fuZZls69pKTnL/0vjD7SKXLNIiqAQ+jRuaMtjIFOcqM0SPB+0dQZQGgqL TrvaJQ4F4IG+GPcTUkZOP8HNdD0HDxNoEHpmuqYN0u0AdCXcgPOOkszZE ZqBCNvmSO5DICbljYdq9BT0Da6q1Z2YPbGL1o8m5uJWC5X5CDGKXPrNXp H/6pDajiK4XEpliZYFuYT6SV2MpWr2q+1C6Q2CgyxlqD0Kk4zSKamCwN0 w==; X-CSE-ConnectionGUID: azV2/ZauTKmCDS1RHed6wg== X-CSE-MsgGUID: o48klsifR0CRJlWH28Eljg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="74137879" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137879" X-CSE-ConnectionGUID: X+72DuASRwCkQEFw1+JTdQ== X-CSE-MsgGUID: TvUd4agaQmC4JnhXgS1gYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184275998" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 07/20] i386/cpu: Reorganize dependency check for arch lbr state Date: Fri, 24 Oct 2025 14:56:19 +0800 Message-Id: <20251024065632.1448606-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287839391158500 Content-Type: text/plain; charset="utf-8" The arch lbr state has 2 dependencies: * Arch lbr feature bit (CPUID 0x7.0x0:EDX[bit 19]): This bit also depends on pmu property. Mask it off if pmu is disabled in x86_cpu_expand_features(), so that it is not needed to repeatedly check whether this bit is set as well as pmu is enabled. Note this doesn't need compat option, since even KVM hasn't support arch lbr yet. The supported xstate is constructed based such dependency in cpuid_has_xsave_feature(), so if pmu is disabled and arch lbr bit is masked off, then arch lbr state won't be included in supported xstates. Thus it's safe to drop the check on arch lbr bit in CPUID 0xD encoding. * XSAVES feature bit (CPUID 0xD.0x1.EAX[bit 3]): Arch lbr state is a supervisor state, which requires the XSAVES feature support. Enumerate supported supervisor state based on XSAVES feature bit in x86_cpu_enable_xsave_components(). Then it's safe to drop the check on XSAVES feature support during CPUID 0XD encoding. Suggested-by: Zide Chen Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/cpu.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 236a2f3a9426..5b7a81fcdb1b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8174,16 +8174,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D xsave_area_size(xstate, true); *ecx =3D env->features[FEAT_XSAVE_XSS_LO]; *edx =3D env->features[FEAT_XSAVE_XSS_HI]; - if (kvm_enabled() && cpu->enable_pmu && - (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && - (*eax & CPUID_XSAVE_XSAVES)) { - *ecx |=3D XSTATE_ARCH_LBR_MASK; - } else { - *ecx &=3D ~XSTATE_ARCH_LBR_MASK; - } - } else if (count =3D=3D 0xf && cpu->enable_pmu - && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LB= R)) { - x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; =20 @@ -8902,6 +8892,12 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) =20 mask =3D 0; for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { + /* Skip supervisor states if XSAVES is not supported. */ + if (CPUID_XSTATE_XSS_MASK & (1 << i) && + !(env->features[FEAT_XSAVE] & CPUID_XSAVE_XSAVES)) { + continue; + } + const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; if (cpuid_has_xsave_feature(env, esa)) { mask |=3D (1ULL << i); @@ -9019,11 +9015,13 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **e= rrp) } } =20 - if (!cpu->pdcm_on_even_without_pmu) { + if (!cpu->enable_pmu) { /* PDCM is fixed1 bit for TDX */ - if (!cpu->enable_pmu && !is_tdx_vm()) { + if (!cpu->pdcm_on_even_without_pmu && !is_tdx_vm()) { env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_PDCM; } + + env->features[FEAT_7_0_EDX] &=3D ~CPUID_7_0_EDX_ARCH_LBR; } =20 for (i =3D 0; i < ARRAY_SIZE(feature_dependencies); i++) { --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="74137883" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137883" X-CSE-ConnectionGUID: k+loaOomT4esGWD24LR1Hg== X-CSE-MsgGUID: JXZ5mRxMRDa0NViqr9Tl8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276030" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 08/20] i386/cpu: Drop pmu check in CPUID 0x1C encoding Date: Fri, 24 Oct 2025 14:56:20 +0800 Message-Id: <20251024065632.1448606-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287774618158501 Content-Type: text/plain; charset="utf-8" Since CPUID_7_0_EDX_ARCH_LBR will be masked off if pmu is disabled, there's no need to check CPUID_7_0_EDX_ARCH_LBR feature with pmu. Tested-by: Farrah Chen Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5b7a81fcdb1b..5cd335bb5574 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8275,11 +8275,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } break; } - case 0x1C: - if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { - x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); - *edx =3D 0; + case 0x1C: /* Last Branch Records Information Leaf */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { + break; } + x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); + *edx =3D 0; /* EDX is reserved. */ break; case 0x1D: { /* AMX TILE, for now hardcoded for Sapphire Rapids*/ --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="74137888" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137888" X-CSE-ConnectionGUID: nKAAY43bRoCSRywEKzFVvA== X-CSE-MsgGUID: nVLkiWPbQ++CaQKbs7y7uQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276057" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 09/20] i386/cpu: Fix supervisor xstate initialization Date: Fri, 24 Oct 2025 14:56:21 +0800 Message-Id: <20251024065632.1448606-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287774601158501 Content-Type: text/plain; charset="utf-8" From: Chao Gao Arch lbr is a supervisor xstate, but its area is not covered in x86_cpu_init_xsave(). Fix it by checking supported xss bitmap. In addition, drop the (uint64_t) type casts for supported_xcr0 since x86_cpu_get_supported_feature_word() returns uint64_t so that the cast is not needed. Then ensure line length is within 90 characters. Tested-by: Farrah Chen Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- target/i386/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5cd335bb5574..1917376dbea9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9707,20 +9707,23 @@ static void x86_cpu_post_initfn(Object *obj) static void x86_cpu_init_xsave(void) { static bool first =3D true; - uint64_t supported_xcr0; + uint64_t supported_xcr0, supported_xss; int i; =20 if (first) { first =3D false; =20 supported_xcr0 =3D - ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAV= E_XCR0_HI) << 32) | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) | x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); + supported_xss =3D + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_HI) <<= 32 | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_LO); =20 for (i =3D XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { ExtSaveArea *esa =3D &x86_ext_save_areas[i]; =20 - if (!(supported_xcr0 & (1 << i))) { + if (!((supported_xcr0 | supported_xss) & (1 << i))) { esa->size =3D 0; } } --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287776; cv=none; d=zohomail.com; s=zohoarc; b=hO9O4cjpd0RDrHc/TfdtX+BoB8KsL6kN8EwRX67nCelvJdnO/TSKlNUQ5oWD8SIORukSe4BZvvh843iSG0T8vuSFwzoYCbTzmDbdjmXXVjkoaGDnsUkW9hzHnvZYkJGRvO2YVSb+FuV4K2qb8lzvk8d3o7ulKwVKUBZ81q7kCCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761287776; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: AEUk+y4fT52k7fLQJR8Y6g== X-CSE-MsgGUID: kFxMChShQimR3bbxMo5ZTw== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="74137891" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="74137891" X-CSE-ConnectionGUID: zdda8MoeRuaoDINh3c/nxA== X-CSE-MsgGUID: mKBG2dchQsOb/9ZT/rM9Xg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276073" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 10/20] i386/cpu: Add missing migratable xsave features Date: Fri, 24 Oct 2025 14:56:22 +0800 Message-Id: <20251024065632.1448606-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287780678158500 Content-Type: text/plain; charset="utf-8" Xtile-cfg & xtile-data are both user xstates. Their xstates are cached in X86CPUState, and there's a related vmsd "vmstate_amx_xtile", so that it's safe to mark them as migratable. Arch lbr xstate is a supervisor xstate, and it is save & load by saving & loading related arch lbr MSRs, which are cached in X86CPUState, and there's a related vmsd "vmstate_arch_lbr". So it's also safe to mark it as migratable (even though KVM hasn't supported it - its migration support is completed in QEMU). PT is still unmigratable since KVM disabled it and there's no vmsd and no other emulation/simulation support. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1917376dbea9..b01729ad36d2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1522,7 +1522,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | - XSTATE_PKRU_MASK, + XSTATE_PKRU_MASK | XSTATE_ARCH_LBR_MASK | XSTATE_XTILE_CFG_MAS= K | + XSTATE_XTILE_DATA_MASK, }, [FEAT_XSAVE_XCR0_HI] =3D { .type =3D CPUID_FEATURE_WORD, --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="184276083" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu , Yang Weijiang Subject: [PATCH v3 11/20] i386/cpu: Enable xsave support for CET states Date: Fri, 24 Oct 2025 14:56:23 +0800 Message-Id: <20251024065632.1448606-12-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287817124158500 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang Add CET_U/S bits in xstate area and report support in xstate feature mask. MSR_XSS[bit 11] corresponds to CET user mode states. MSR_XSS[bit 12] corresponds to CET supervisor mode states. CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) features are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX[7] and EDX[20] respectively, two features share the same state bits in XSS, so if either of the features is enabled, set CET_U and CET_S bits together. Tested-by: Farrah Chen Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v2: - Rename XSavesCETU/XSavesCETS to XSaveCETU/XSaveCETS. - Refine the comments. - Drop ".offset =3D 0" and its comment. - Re-describe xstate dependencies via features array. - Drop "cet-u" & "cet-s" enumeration from FEAT_XSAVE_XSS_LO's feat_name array sicne currently xsave doesn't use named features. --- target/i386/cpu.c | 14 ++++++++++++++ target/i386/cpu.h | 26 +++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b01729ad36d2..0bb65e8c5321 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2078,6 +2078,20 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU }, }, }, + [XSTATE_CET_U_BIT] =3D { + .size =3D sizeof(XSaveCETU), + .features =3D { + { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK }, + { FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT }, + }, + }, + [XSTATE_CET_S_BIT] =3D { + .size =3D sizeof(XSaveCETS), + .features =3D { + { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK }, + { FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT }, + }, + }, [XSTATE_ARCH_LBR_BIT] =3D { .size =3D sizeof(XSaveArchLBR), .features =3D { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6537affcf067..7584cddb5917 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -589,6 +589,8 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PT_BIT 8 #define XSTATE_PKRU_BIT 9 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 #define XSTATE_ARCH_LBR_BIT 15 #define XSTATE_XTILE_CFG_BIT 17 #define XSTATE_XTILE_DATA_BIT 18 @@ -603,6 +605,8 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PT_MASK (1ULL << XSTATE_PT_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) @@ -625,7 +629,8 @@ typedef enum X86Seg { XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA= _MASK) =20 /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) +#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK | XSTATE_CET_U_MASK = | \ + XSTATE_CET_S_MASK) =20 #define CPUID_XSTATE_MASK (CPUID_XSTATE_XCR0_MASK | CPUID_XSTATE_XSS= _MASK) =20 @@ -904,6 +909,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* Control-flow enforcement technology: shadow stack */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -951,6 +958,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) /* Architectural LBRs */ #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) +/* Control-flow enforcement technology: indirect branch tracking */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* AMX_BF16 instruction */ #define CPUID_7_0_EDX_AMX_BF16 (1U << 22) /* AVX512_FP16 instruction */ @@ -1737,6 +1746,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: CET_U state */ +typedef struct XSaveCETU { + uint64_t u_cet; + uint64_t pl3_ssp; +} XSaveCETU; + +/* Ext. save area 12: CET_S state */ +typedef struct XSaveCETS { + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSaveCETS; + /* Ext. save area 15: Arch LBR state */ typedef struct XSaveArchLBR { uint64_t lbr_ctl; @@ -1764,6 +1786,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveCETU) !=3D 0x10); +QEMU_BUILD_BUG_ON(sizeof(XSaveCETS) !=3D 0x18); QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="184276091" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 12/20] i386/cpu: Add CET support in CR4 Date: Fri, 24 Oct 2025 14:56:24 +0800 Message-Id: <20251024065632.1448606-13-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287815013158500 Content-Type: text/plain; charset="utf-8" CR4.CET bit (bit 23) is as master enable for CET. Check and adjust CR4.CET bit based on CET CPUIDs. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.h | 7 ++++++- target/i386/helper.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7584cddb5917..86fbfd5e4023 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -257,6 +257,7 @@ typedef enum X86Seg { #define CR4_SMEP_MASK (1U << 20) #define CR4_SMAP_MASK (1U << 21) #define CR4_PKE_MASK (1U << 22) +#define CR4_CET_MASK (1U << 23) #define CR4_PKS_MASK (1U << 24) #define CR4_LAM_SUP_MASK (1U << 28) =20 @@ -274,7 +275,7 @@ typedef enum X86Seg { | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_M= ASK \ - | CR4_LAM_SUP_MASK | CR4_FRED_MASK)) + | CR4_LAM_SUP_MASK | CR4_FRED_MASK | CR4_CET_MASK)) =20 #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2945,6 +2946,10 @@ static inline uint64_t cr4_reserved_bits(CPUX86State= *env) if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { reserved_bits |=3D CR4_FRED_MASK; } + if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + !(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) { + reserved_bits |=3D CR4_CET_MASK; + } return reserved_bits; } =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 72b2e195a31e..3f179c6c11f8 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -232,6 +232,18 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new= _cr4) new_cr4 &=3D ~CR4_LAM_SUP_MASK; } =20 + /* + * In fact, "CR4.CET can be set only if CR0.WP is set, and it must be + * clear before CR0.WP can be cleared". However, here we only check + * CR4.CET based on the supported CPUID CET bit, without checking the + * dependency on CR4.WP - the latter need to be determined by the + * underlying accelerators. + */ + if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + !(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) { + new_cr4 &=3D ~CR4_CET_MASK; + } + env->cr[4] =3D new_cr4; env->hflags =3D hflags; =20 --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287801; cv=none; d=zohomail.com; s=zohoarc; b=TknnWl2NMpQOMcI/aso/q8npC/7YixLvLo539TnQ5AEVm7UIBxDOCBpXCO2kLxbuNJrYio3EaMhfH7/wDZcExej8r0WO4ExB8cerw7eH3X7ci/2RhTWpXessLfKmFqEbBe8N6uFeTrfuZSwNsSipmp2BRWyG8bAsGAHrG0L4DpI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287802928158500 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang CET (architectural) MSRs include: MSR_IA32_U_CET - user mode CET control bits. MSR_IA32_S_CET - supervisor mode CET control bits. MSR_IA32_PL{0,1,2,3}_SSP - linear addresses of SSPs for user/kernel modes. MSR_IA32_SSP_TBL_ADDR - linear address of interrupt SSP table Tested-by: Farrah Chen Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v2: - Rename MSR_IA32_SSP_TBL_ADDR to MSR_IA32_INT_SSP_TAB. - Rename X86CPUState.ssp_table_addr to X86CPUState.int_ssp_table. - Drop X86CPUStete.guest_ssp since it is not used in current commit. - Do not check CET-S & CET-U xtates when get/set MSTs since CET is XSAVE-managed feature but is not XSAVE-enabled. --- target/i386/cpu.h | 16 +++++++++++ target/i386/kvm/kvm.c | 64 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 86fbfd5e4023..4edb977575e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -580,6 +580,14 @@ typedef enum X86Seg { #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff =20 +#define MSR_IA32_U_CET 0x000006a0 /* user mode cet = */ +#define MSR_IA32_S_CET 0x000006a2 /* kernel mode ce= t */ +#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow = stack pointer */ +#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow = stack pointer */ +#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow = stack pointer */ +#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow = stack pointer */ +#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shad= ow stack table */ + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -2090,6 +2098,14 @@ typedef struct CPUArchState { uint64_t msr_rapl_power_unit; uint64_t msr_pkg_energy_status; =20 + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; + uint64_t int_ssp_table; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f7a6ef650af7..92c2fd6d6aee 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4255,6 +4255,28 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) } } =20 + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK || + env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + + /* + * This MSR is not present on processors that do not support + * Intel 64 architecture. + */ + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB, + env->int_ssp_table); + } + } + } + return kvm_buf_set_msrs(cpu); } =20 @@ -4646,6 +4668,27 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK || + env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + + /* + * This MSR is not present on processors that do not support + * Intel 64 architecture. + */ + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB, 0); + } + } + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -4993,6 +5036,27 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info =3D msrs[i]= .data; break; + case MSR_IA32_U_CET: + env->u_cet =3D msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet =3D msrs[i].data; + break; + case MSR_IA32_PL0_SSP: + env->pl0_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp =3D msrs[i].data; + break; + case MSR_IA32_INT_SSP_TAB: + env->int_ssp_table =3D msrs[i].data; + break; case MSR_K7_HWCR: env->msr_hwcr =3D msrs[i].data; break; --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="184276104" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu , Yang Weijiang Subject: [PATCH v3 14/20] i386/kvm: Add save/load support for KVM_REG_GUEST_SSP Date: Fri, 24 Oct 2025 14:56:26 +0800 Message-Id: <20251024065632.1448606-15-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287829183158500 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang CET provides a new architectural register, shadow stack pointer (SSP), which cannot be directly encoded as a source, destination or memory operand in instructions. But Intel VMCS & VMCB provide fields to save/load guest & host's ssp. It's necessary to save & load Guest's ssp before & after migration. To support this, KVM implements Guest's SSP as a special KVM internal register - KVM_REG_GUEST_SSP, and allows QEMU to save & load it via KVM_GET_ONE_REG/KVM_SET_ONE_REG. Cache KVM_REG_GUEST_SSP in X86CPUState. Tested-by: Farrah Chen Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/cpu.h | 1 + target/i386/kvm/kvm.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4edb977575e2..ad4287822831 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2105,6 +2105,7 @@ typedef struct CPUArchState { uint64_t pl2_ssp; uint64_t pl3_ssp; uint64_t int_ssp_table; + uint64_t guest_ssp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 92c2fd6d6aee..412e99ba5b53 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4280,6 +4280,35 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) return kvm_buf_set_msrs(cpu); } =20 +static int kvm_put_kvm_regs(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + int ret; + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + ret =3D kvm_set_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SS= P), + &env->guest_ssp); + if (ret) { + return ret; + } + } + return 0; +} + +static int kvm_get_kvm_regs(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + int ret; + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + ret =3D kvm_get_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SS= P), + &env->guest_ssp); + if (ret) { + return ret; + } + } + return 0; +} =20 static int kvm_get_xsave(X86CPU *cpu) { @@ -5425,6 +5454,11 @@ int kvm_arch_put_registers(CPUState *cpu, KvmPutStat= e level, Error **errp) error_setg_errno(errp, -ret, "Failed to set MSRs"); return ret; } + ret =3D kvm_put_kvm_regs(x86_cpu); + if (ret < 0) { + error_setg_errno(errp, -ret, "Failed to set KVM type registers"); + return ret; + } ret =3D kvm_put_vcpu_events(x86_cpu, level); if (ret < 0) { error_setg_errno(errp, -ret, "Failed to set vCPU events"); @@ -5497,6 +5531,11 @@ int kvm_arch_get_registers(CPUState *cs, Error **err= p) error_setg_errno(errp, -ret, "Failed to get MSRs"); goto out; } + ret =3D kvm_get_kvm_regs(cpu); + if (ret < 0) { + error_setg_errno(errp, -ret, "Failed to get KVM type registers"); + goto out; + } ret =3D kvm_get_apic(cpu); if (ret < 0) { error_setg_errno(errp, -ret, "Failed to get APIC"); --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287783; cv=none; d=zohomail.com; s=zohoarc; b=Wb/c8ljaEgWmyfuroDMCvv21fZtnFbuCuMorvEdt80tdZ50/IhMtlaNOIjqljCsfmUGCxH9YN+BVHAMUYO5qnI3wXvGYOA+nDNAzT9nPQDOH5PhfUb66yVCbmZUPOwlEBWY9YSB3XEWoKlUAFrLyYPsA0qQmv5wS1FYnysMl2k4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761287783; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: JcpOqBufSN+z1nFw1VwAPw== X-CSE-MsgGUID: L9rtiwlPSAWck3p/TbtfGA== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63170923" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="63170923" X-CSE-ConnectionGUID: WloA9umMSkm/n6Cz1qupVg== X-CSE-MsgGUID: LIouHQykSIytxUQS4lRFKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276114" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu , Yang Weijiang Subject: [PATCH v3 15/20] i386/machine: Add vmstate for cet-ss and cet-ibt Date: Fri, 24 Oct 2025 14:56:27 +0800 Message-Id: <20251024065632.1448606-16-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287790740158500 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang Add vmstates for cet-ss and cet-ibt Tested-by: Farrah Chen Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v2: - Split a subsection "vmstate_ss" since shstk is user-configurable. --- target/i386/machine.c | 53 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 45b7cea80aa7..3ad07ec82428 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1668,6 +1668,58 @@ static const VMStateDescription vmstate_triple_fault= =3D { } }; =20 +static bool shstk_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK); +} + +static const VMStateDescription vmstate_ss =3D { + .name =3D "cpu/cet_ss", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D shstk_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_UINT64(env.pl1_ssp, X86CPU), + VMSTATE_UINT64(env.pl2_ssp, X86CPU), + VMSTATE_UINT64(env.pl3_ssp, X86CPU), +#ifdef TARGET_X86_64 + /* This MSR is only present on Intel 64 architecture. */ + VMSTATE_UINT64(env.int_ssp_table, X86CPU), +#endif + VMSTATE_UINT64(env.guest_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)); +} + +static const VMStateDescription vmstate_cet =3D { + .name =3D "cpu/cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.u_cet, X86CPU), + VMSTATE_UINT64(env.s_cet, X86CPU), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_ss, + NULL, + }, +}; + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1817,6 +1869,7 @@ const VMStateDescription vmstate_x86_cpu =3D { #endif &vmstate_arch_lbr, &vmstate_triple_fault, + &vmstate_cet, NULL } }; --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287859; cv=none; d=zohomail.com; s=zohoarc; b=CdAoHkIaVZZ00SKuJWvBOSp9lZnIB79IxZIV3FH949tgGUMy0Tm30PReOgNIaqShKH8T6FzTx8UM1qrWPuMcB21heseGsaLfkDcyJBFc0DT55f6lLLDRyrUs/0ixA1pCzrgGgasep8PaGFOgq1xcP8oJ7/WTaNQJwQDNtM/rDiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761287859; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: WdATN3D6T/ufnomq5VtD/g== X-CSE-MsgGUID: xoePEppfSlCkXUBlZJdGfQ== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63170925" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="63170925" X-CSE-ConnectionGUID: jRolYxpvRZSQV73Acdf+Eg== X-CSE-MsgGUID: CE6ftexvT6uoAXJnvCnNIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276120" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 16/20] i386/cpu: Mark cet-u & cet-s xstates as migratable Date: Fri, 24 Oct 2025 14:56:28 +0800 Message-Id: <20251024065632.1448606-17-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287861762158502 Content-Type: text/plain; charset="utf-8" Cet-u and cet-s are supervisor xstates. Their states are saved/loaded by saving/loading related CET MSRs. And there's a vmsd "vmstate_cet" to migrate these MSRs. Thus, it's safe to mark them as migratable. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0bb65e8c5321..c08066a338a3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1522,7 +1522,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | - XSTATE_PKRU_MASK | XSTATE_ARCH_LBR_MASK | XSTATE_XTILE_CFG_MAS= K | + XSTATE_PKRU_MASK | XSTATE_CET_U_MASK | XSTATE_CET_S_MASK | + XSTATE_ARCH_LBR_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK, }, [FEAT_XSAVE_XCR0_HI] =3D { --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="184276135" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu , Yang Weijiang Subject: [PATCH v3 17/20] i386/cpu: Advertise CET related flags in feature words Date: Fri, 24 Oct 2025 14:56:29 +0800 Message-Id: <20251024065632.1448606-18-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287790785158500 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang Add SHSTK and IBT flags in feature words with entry/exit control flags. CET SHSTK and IBT feature are enumerated via CPUID(EAX=3D7,ECX=3D0) ECX[bit 7] and EDX[bit 20]. CET states load/restore at vmentry/ vmexit are controlled by VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28]. Enable these flags so that KVM can enumerate the features properly. Tested-by: Farrah Chen Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v2: - Rename "shstk"/"ibt" to "cet-ss"/"cet-ibt" to match feature names in SDM & APM. - Rename "vmx-exit-save-cet-ctl"/"vmx-entry-load-cet-ctl" to "vmx-exit-save-cet"/"vmx-entry-load-cet". - Define the feature mask macro for easier double check. --- target/i386/cpu.c | 8 ++++---- target/i386/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c08066a338a3..9a1001c47891 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1221,7 +1221,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", "cet-ss", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -1244,7 +1244,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", - NULL, NULL, "amx-bf16", "avx512-fp16", + "cet-ibt", NULL, "amx-bf16", "avx512-fp16", "amx-tile", "amx-int8", "spec-ctrl", "stibp", "flush-l1d", "arch-capabilities", "core-capability", "ssbd", }, @@ -1666,7 +1666,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", + "vmx-exit-save-cet", "vmx-exit-load-pkrs", NULL, "vmx-exit-sec= ondary-ctls", }, .msr =3D { .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, @@ -1681,7 +1681,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, "vmx-entry-ia32e-mode", NULL, NULL, NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat",= "vmx-entry-load-efer", "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NUL= L, - NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", + "vmx-entry-load-cet", NULL, "vmx-entry-load-pkrs", "vmx-entry-= load-fred", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ad4287822831..fa3e5d87fe50 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1369,6 +1369,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 +#define VMX_VM_EXIT_SAVE_CET 0x10000000 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 =20 @@ -1382,6 +1383,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 +#define VMX_VM_ENTRY_LOAD_CET 0x00100000 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 =20 /* Supported Hyper-V Enlightenments */ --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="184276147" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 18/20] i386/cpu: Enable cet-ss & cet-ibt for supported CPU models Date: Fri, 24 Oct 2025 14:56:30 +0800 Message-Id: <20251024065632.1448606-19-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287845417158500 Content-Type: text/plain; charset="utf-8" Add new versioned CPU models for Sapphire Rapids, Sierra Forest, Granite Rapids and Clearwater Forest, to enable shadow stack and indirect branch tracking. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9a1001c47891..73026d5bce91 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5161,6 +5161,17 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ }, } }, + { + .version =3D 5, + .note =3D "with cet-ss and cet-ibt", + .props =3D (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ } } }, @@ -5323,6 +5334,17 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ }, } }, + { + .version =3D 4, + .note =3D "with cet-ss and cet-ibt", + .props =3D (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, @@ -5477,6 +5499,17 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ }, } }, + { + .version =3D 4, + .note =3D "with cet-ss and cet-ibt", + .props =3D (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, @@ -5612,6 +5645,17 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .model_id =3D "Intel Xeon Processor (ClearwaterForest)", .versions =3D (X86CPUVersionDefinition[]) { { .version =3D 1 }, + { + .version =3D 2, + .note =3D "with cet-ss and cet-ibt", + .props =3D (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="63170937" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="63170937" X-CSE-ConnectionGUID: 6/Du4PsrQKecWwQXOAn6HQ== X-CSE-MsgGUID: 76V0wjcmSm6iWeeDdSD99g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276158" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 19/20] i386/tdx: Fix missing spaces in tdx_xfam_deps[] Date: Fri, 24 Oct 2025 14:56:31 +0800 Message-Id: <20251024065632.1448606-20-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287802957158500 Content-Type: text/plain; charset="utf-8" The checkpatch.pl always complains: "ERROR: space required after that close brace '}'". Fix this issue. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/kvm/tdx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index dbf0fa2c9180..a3444623657f 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -520,15 +520,15 @@ typedef struct TdxXFAMDep { * supported. */ TdxXFAMDep tdx_xfam_deps[] =3D { - { XSTATE_YMM_BIT, { FEAT_1_ECX, CPUID_EXT_FMA }}, - { XSTATE_YMM_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 }}, - { XSTATE_OPMASK_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI}}, - { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16}}, - { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT}}, - { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU}}, - { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 }}, - { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }}, - { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 }}, + { XSTATE_YMM_BIT, { FEAT_1_ECX, CPUID_EXT_FMA } }, + { XSTATE_YMM_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 } }, + { XSTATE_OPMASK_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI } }, + { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16 } }, + { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT } }, + { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 } }, }; =20 static struct kvm_cpuid_entry2 *find_in_supported_entry(uint32_t function, --=20 2.34.1 From nobody Mon Oct 27 11:31:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1761287818; cv=none; d=zohomail.com; s=zohoarc; b=Xu9IVHZaTnoVVE3SAGkPuLXkXxACaIJq0QgOBLuKlxXZTy5ocMXdaZ+XRdXJtkvNVNiflMWZhdPL+amYRka+2neg+f+UQeNeT4IjBJhDheoOiSb4nKp85Dy4EQZo3KW0qfcCIdIjv+sNc0h6mZxtsE+mpkjoQ5fWB1kxrMno7E8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761287818; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: xO6f5wZjQduzskT+7pM5Pg== X-CSE-MsgGUID: JQrCtSMXQtOCl6BnZScTCg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="51044395" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="51044395" X-CSE-ConnectionGUID: gOpFmPulTYawoqbWtdGs6Q== X-CSE-MsgGUID: CoV1hSAoSN+SYf2/kQ6vuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276197" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 20/20] i386/tdx: Add CET SHSTK/IBT into the supported CPUID by XFAM Date: Fri, 24 Oct 2025 14:56:32 +0800 Message-Id: <20251024065632.1448606-21-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761287821284158500 Content-Type: text/plain; charset="utf-8" From: Chenyi Qiang So that it can be configured in TD guest. And considerring cet-u and cet-s have the same dependencies, it's enough to only list cet-u in tdx_xfam_deps[]. Tested-by: Farrah Chen Signed-off-by: Chenyi Qiang Signed-off-by: Zhao Liu --- target/i386/kvm/tdx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index a3444623657f..01619857685b 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -526,6 +526,8 @@ TdxXFAMDep tdx_xfam_deps[] =3D { { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16 } }, { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT } }, { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU } }, + { XSTATE_CET_U_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK } }, + { XSTATE_CET_U_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT } }, { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 } }, { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE } }, { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 } }, --=20 2.34.1