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d="scan'208";a="183554351" From: Zhao Liu To: Paolo Bonzini , Manos Pitsidianakis Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Zhao Liu Subject: [PATCH v2] rust/qemu-macros: Convert bit value to u8 within #[property] Date: Fri, 24 Oct 2025 12:13:44 +0800 Message-Id: <20251024041344.1389488-1-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761277980091158500 Content-Type: text/plain; charset="utf-8" For bit property, make the type conversion within the #[property] macro so that users do not need to handle the conversion. Suggested-by: Paolo Bonzini Signed-off-by: Zhao Liu Reviewed-by: Manos Pitsidianakis --- Changes Since v2: - Check #field_ty::BITS instead of u8::MAX. - Update test cases. --- rust/hw/timer/hpet/src/device.rs | 2 +- rust/qemu-macros/src/lib.rs | 23 ++++++++++++++++++----- rust/qemu-macros/src/tests.rs | 15 ++++++++++++--- 3 files changed, 31 insertions(+), 9 deletions(-) diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/devi= ce.rs index 86638c076666..23f2eefd1cd9 100644 --- a/rust/hw/timer/hpet/src/device.rs +++ b/rust/hw/timer/hpet/src/device.rs @@ -539,7 +539,7 @@ pub struct HPETState { // Internal state /// Capabilities that QEMU HPET supports. /// bit 0: MSI (or FSB) support. - #[property(rename =3D "msi", bit =3D HPET_FLAG_MSI_SUPPORT_SHIFT as u8= , default =3D false)] + #[property(rename =3D "msi", bit =3D HPET_FLAG_MSI_SUPPORT_SHIFT, defa= ult =3D false)] flags: u32, =20 /// Offset of main counter relative to qemu clock. diff --git a/rust/qemu-macros/src/lib.rs b/rust/qemu-macros/src/lib.rs index 50239f228be2..ee417bb4b4ef 100644 --- a/rust/qemu-macros/src/lib.rs +++ b/rust/qemu-macros/src/lib.rs @@ -262,12 +262,25 @@ macro_rules! str_to_c_str { }, )?; let field_ty =3D field.ty.clone(); - let qdev_prop =3D if bitnr.is_none() { - quote! { <#field_ty as ::hwcore::QDevProp>::BASE_INFO } + let (qdev_prop, bitval) =3D if let Some(bitval) =3D bitnr { + ( + quote! { <#field_ty as ::hwcore::QDevProp>::BIT_INFO }, + quote! { + { + const { + assert!(#bitval >=3D 0 && #bitval < #field_ty:= :BITS as _, + "bit number exceeds type bits range"); + } + #bitval as u8 + } + }, + ) } else { - quote! { <#field_ty as ::hwcore::QDevProp>::BIT_INFO } + ( + quote! { <#field_ty as ::hwcore::QDevProp>::BASE_INFO }, + quote! { 0 }, + ) }; - let bitnr =3D bitnr.unwrap_or(syn::Expr::Verbatim(quote! { 0 })); let set_default =3D defval.is_some(); let defval =3D defval.unwrap_or(syn::Expr::Verbatim(quote! { 0 })); properties_expanded.push(quote! { @@ -275,7 +288,7 @@ macro_rules! str_to_c_str { name: ::std::ffi::CStr::as_ptr(#prop_name), info: #qdev_prop, offset: ::core::mem::offset_of!(#name, #field_name) as isi= ze, - bitnr: #bitnr, + bitnr: #bitval, set_default: #set_default, defval: ::hwcore::bindings::Property__bindgen_ty_1 { u: #d= efval as u64 }, ..::common::Zeroable::ZERO diff --git a/rust/qemu-macros/src/tests.rs b/rust/qemu-macros/src/tests.rs index 65691412ff57..b65cf656fa36 100644 --- a/rust/qemu-macros/src/tests.rs +++ b/rust/qemu-macros/src/tests.rs @@ -179,7 +179,10 @@ unsafe impl ::hwcore::DevicePropertiesImpl for DummySt= ate { name: ::std::ffi::CStr::as_ptr(c"flags"), info: ::BIT_INFO, offset: ::core::mem::offset_of!(DummyState, flags)= as isize, - bitnr: 3, + bitnr : { + const { assert!(3 >=3D 0 && 3 < u32::BITS as _= , "bit number exceeds type bits range"); } + 3 as u8 + }, set_default: false, defval: ::hwcore::bindings::Property__bindgen_ty_1= { u: 0 as u64 }, ..::common::Zeroable::ZERO @@ -207,7 +210,10 @@ unsafe impl ::hwcore::DevicePropertiesImpl for DummySt= ate { name: ::std::ffi::CStr::as_ptr(c"flags"), info: ::BIT_INFO, offset: ::core::mem::offset_of!(DummyState, flags)= as isize, - bitnr: 3, + bitnr : { + const { assert!(3 >=3D 0 && 3 < u32::BITS as _= , "bit number exceeds type bits range"); } + 3 as u8 + }, set_default: true, defval: ::hwcore::bindings::Property__bindgen_ty_1= { u: true as u64 }, ..::common::Zeroable::ZERO @@ -235,7 +241,10 @@ unsafe impl ::hwcore::DevicePropertiesImpl for DummySt= ate { name: ::std::ffi::CStr::as_ptr(c"msi"), info: ::BIT_INFO, offset: ::core::mem::offset_of!(DummyState, flags)= as isize, - bitnr: 3, + bitnr : { + const { assert!(3 >=3D 0 && 3 < u64::BITS as _= , "bit number exceeds type bits range"); } + 3 as u8 + }, set_default: true, defval: ::hwcore::bindings::Property__bindgen_ty_1= { u: false as u64 }, ..::common::Zeroable::ZERO --=20 2.34.1