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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429898acc63sm4398465f8f.27.2025.10.23.07.56.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Oct 2025 07:56:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1761231372; x=1761836172; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=F0pSAJ7AP3EIbBDaOPx9w3eo4OwQ/YGmc/QOEJCgnxg=; b=iQEdOkc9qPFbKvtYW/DlCUrib7s3HNyCyTd2fsESerjtPIuneI0IwXwonqgiW/pVcf L5AYjSQ+YSn4u5ueqy+F8yP5gE2IpFbls7jmmVjyQ+qH08gSHFrpRH0Mf2JXjnbUReTJ Ho98DXRkyPGUJOdwaqGZqO7xYNpzJCkEdr+Mb9AqGhqfUEYDpxbrv1CinnNYzR8rRonH sPdRhdFi/Y8oRABNdLQ1Eg3xTEcn0eutlMlf8za3ceeoS8HIqHl462QK3jCBj0eGyXM1 m12jujCZEshdSJ/gyAqOHJH0lBejHBmmcOoA1iJy2Lluo9GVK+Z6AtjQCNjN4IGQP37N UfLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761231372; x=1761836172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F0pSAJ7AP3EIbBDaOPx9w3eo4OwQ/YGmc/QOEJCgnxg=; b=j8N29QHHaclJiJjzU8MCSMyX8i9/q5cbXdbEiNYzXd52vNpQYRtqPQfSJ4OBQNPX2h 6NnVGswGQBAo8KeTLGKFnOGTdNaDZCHad87+yjbakmG5I03ALcz9AGWXNZXeKjvgqGdS cPEtR9GiIJ2vN89tjtdEP0wpWDgl9Xqqq5bduC5yqyafUBDZQMQKIU1bPotDxHORDZwG yxQGdk463WZX1PMEtk0IDVYn8c9PL59/tR039YHSt9/vl9f4yUZcqV2QmDRQp2AuFK9G H9xPhQyr9yYgVQ1VAUn2UsjaA1/1i3/H+UAoXYalDnsvaelSfWZ1fvlLQicC3AgrQ3OG i+Zg== X-Gm-Message-State: AOJu0Yxat3mjrPc5ou1C44egWCLejH0MzmBMcSpP4vA+LEpGR7QMnPow SlaCqiNyBCy7xexDcFDvDn+wSnec8BHx3wvdZA6a9N+amBT56TooUCTM1bNm9XExTnwK+n6inwQ SrXsm X-Gm-Gg: ASbGncsK/0lCAWlfaD1Yj0PDXk7edBQeliOB9TQPXAaDf1mh6GWA0uFqyfIG3fgj1dB LXLeRybRbSKcLo/daWSvU7SMVwJMERHIMBite4WhspwDBxydPr1zplj4BtWKsNY7ImVhsUDE4oo fRbe2udwbBpicu58OAEUUIhot8p/DxgfcwJJc9OQEflzyEmlTH+GSt1dVbOxiAWt27O+ZaVM0hE yz6CCO0VwH311N0jdcUPIhb2XrGCT7ug1lBgzLgBayBV6vD8fCbVqVlqLNurFFQ0QcQITysd4vY NjV3LbjndemYn3lmnMmN7Z+0fg3eKdyccGFj89dIzZVLptDSYEPD7BFE2i/ahDBRF3sJ4LS0xOH wTXGM058UoH6K2xciCMUZpnof7/vapeNbomAwFPN21yIiu+Yn5p1fwZE0J8UJJqdsijBD/RISbC Kok0yCiA== X-Google-Smtp-Source: AGHT+IH3liUeNlYpuoHGcKnshekwTa/6uKIeUzihoMjHp9CC4P2AgyT56Iq61PCY3tj4jxfKi9FJDQ== X-Received: by 2002:a05:600c:628f:b0:468:9e79:bee0 with SMTP id 5b1f17b1804b1-475caed394dmr20565595e9.0.1761231371747; Thu, 23 Oct 2025 07:56:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/16] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub Date: Thu, 23 Oct 2025 15:55:52 +0100 Message-ID: <20251023145554.2062752-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023145554.2062752-1-peter.maydell@linaro.org> References: <20251023145554.2062752-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1761231446175154100 Content-Type: text/plain; charset="utf-8" GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls, which will contain either just "tpidr", or else "tpidr" and "tpidr2". This will be important for SME in future, because the lazy state restoration scheme requires GDB to use the TPIDR2 information. GDB doesn't currently implement that, but we should provide the register via the XML so that we are ready when future GDB versions support it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20251017153027.969016-3-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 6 ++++ target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7c226a112d5..39f2b2e54de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -943,6 +943,7 @@ struct ArchCPU { DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; + DynamicGDBFeatureInfo dyn_tls_feature; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/internals.h b/target/arm/internals.h index bf44066f71b..f86f421a3db 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1716,6 +1716,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *= env) =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); @@ -1728,6 +1729,8 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArra= y *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1ca3e647a84..8865f27089d 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -583,6 +583,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) 0); } #endif + + /* All AArch64 CPUs have at least TPIDR */ + gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg, + aarch64_gdb_set_tls_reg, + arm_gen_dynamic_tls_feature(cs, cs->gdb_n= um_regs), + 0); #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 5ad00fe771d..3bc7ff45d57 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -387,6 +387,44 @@ int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *bu= f, int reg) return 0; } =20 +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr_el[0]); + case 1: /* TPIDR2_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr2_el0); + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + env->cp15.tpidr_el[0] =3D ldq_p(buf); + return 8; + case 1: /* TPIDR2_EL0 */ + env->cp15.tpidr2_el0 =3D ldq_p(buf); + return 8; + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -586,6 +624,31 @@ GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_smereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_tls_feature.desc, + "org.gnu.gdb.aarch64.tls", "tls-registers.xml= ", + base_reg); + + /* + * This feature must always have "tpidr", and may also have "tpidr2" + * if the CPU has that register. + */ + gdb_feature_builder_append_reg(&builder, "tpidr", 64, + reg++, "data_ptr", NULL); + if (cpu_isar_feature(aa64_sme, cpu)) { + gdb_feature_builder_append_reg(&builder, "tpidr2", 64, + reg++, "data_ptr", NULL); + } + gdb_feature_builder_end(&builder); + + return &cpu->dyn_tls_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { --=20 2.43.0