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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=a.aliokhin@syntacore.com; helo=m.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 23 Oct 2025 08:24:30 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1761222967990154100 Content-Type: text/plain; charset="utf-8" cs.w and sc.d instructions should throw a "Load/Save/AMO address misaligned" exception when this happens, but they don't. Fix solves this issue. Note: When using misaligned address sc.w and sc.d commands always skip store phase because either there was no corresponding lr.w or lr.d command or there was a corresponding command with an unaligned address or there was mismatched command with a completely different address. In either case, the reservation set did not match the address and command goes to final step to invalidate reservation set. According specification all sc commands always must first invalidate reservation set (if any) and then complete execution normally or by throwing an exception Signed-off-by: Andrey Alekhin --- target/riscv/insn_trans/trans_rva.c.inc | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 9cf3ae8019..93b89866ae 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -57,9 +57,10 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Mem= Op mop) =20 static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv dest, src1, src2; + TCGv dest, src1, src2, mc; TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); + TCGLabel *l3 =3D gen_new_label(); =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); @@ -93,6 +94,26 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Mem= Op mop) */ tcg_gen_movi_tl(load_res, -1); =20 + mc =3D tcg_constant_tl((1 << (mop & MO_SIZE)) - 1); + /* + * When using misaligned address sc.w and sc.d commands + * always skip store phase because either there was + * no corresponding lr.w or lr.d command or there was + * a corresponding command with an unaligned address + * or there was mismatched command with a completely different + * address. + * In either case, the reservation set did not match the + * address and command goes to final step to invalidate + * reservation set. According specification all sc commands + * always must first invalidate reservation set (if any) + * and then complete execution normally or by throwing + * an exception + */ + tcg_gen_brcond_tl(TCG_COND_TSTEQ, src1, mc, l3); + gen_helper_raise_exception(tcg_env, + tcg_constant_i32(RISCV_EXCP_STORE_AMO_ADDR_MIS)); + + gen_set_label(l3); return true; } =20 --=20 2.43.0