From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213773; cv=none; d=zohomail.com; s=zohoarc; b=i6bCmkZZY+mxh6HbIU3/AS1xyHvxI6zxdbhTBKq+RjCheDy77KvNswIGnkhP2Drpad40MO1wch78KOFUskPVah9+JhV1t3MV+Oj1wVk9BHHAgkNE3k5n12FGBSLNVj+CeEMgA5B6yo4T+z+MOzd/ZhSDLcmt9zY9uqtbLMZrfKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213773; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=EGEVHM1j82kuPTF/Oe6RP04hKK8OlBCUjEWqnYBThLs=; b=VoH5cgIQn/3xRK2Njv6UKvEl+ZTuGNb+WAVqYEuGvkVNw6jzkcYzTzj6CYbx51CIoK4RbMcS6XE1m8KvS6ygOSZUBR80672gm8z5jgXIcb2leQolLXsXWMiW6UkmXaxglojZ5ZsnNb0YH5NJK4mCgDzz9zGd03QylTocGizMBhs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761213773611869.0369858419109; Thu, 23 Oct 2025 03:02:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9L-0001LM-NA; Thu, 23 Oct 2025 06:02:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs8z-0001Go-Gh; Thu, 23 Oct 2025 06:02:07 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs8x-00039r-Vb; Thu, 23 Oct 2025 06:02:05 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:51 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:51 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 01/13] hw/arm/aspeed: Move AspeedMachineState definition to common header for reuse Date: Thu, 23 Oct 2025 18:01:34 +0800 Message-ID: <20251023100150.295370-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213777365158500 Content-Type: text/plain; charset="utf-8" Aspeed machines will be moved into split C files for better modularization and future maintenance. To allow all machine implementations to reuse the same AspeedMachineState structure, the struct definition is moved from aspeed.c to the shared header aspeed.h. This change centralizes the common state structure used across all Aspeed machine models, reduces redundancy, and simplifies future refactoring work for new machines. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed.h | 14 ++++++++++++++ hw/arm/aspeed.c | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 6c36455656..383ebb9759 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -11,6 +11,7 @@ =20 #include "hw/boards.h" #include "qom/object.h" +#include "hw/arm/aspeed_soc.h" =20 typedef struct AspeedMachineState AspeedMachineState; =20 @@ -24,6 +25,19 @@ DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineCl= ass, #define ASPEED_MAC2_ON (1 << 2) #define ASPEED_MAC3_ON (1 << 3) =20 +struct AspeedMachineState { + /* Private */ + MachineState parent_obj; + /* Public */ + + AspeedSoCState *soc; + MemoryRegion boot_rom; + bool mmio_exec; + uint32_t uart_chosen; + char *fmc_model; + char *spi_model; + uint32_t hw_strap1; +}; =20 struct AspeedMachineClass { MachineClass parent_obj; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 1bc9e534ba..761b526994 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -35,20 +35,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ }; =20 -struct AspeedMachineState { - /* Private */ - MachineState parent_obj; - /* Public */ - - AspeedSoCState *soc; - MemoryRegion boot_rom; - bool mmio_exec; - uint32_t uart_chosen; - char *fmc_model; - char *spi_model; - uint32_t hw_strap1; -}; - /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ #if HOST_LONG_BITS =3D=3D 32 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213841; cv=none; d=zohomail.com; s=zohoarc; b=kFXMH9isULkypc8UBh4wA7u0cJc871zf8QV1JNRurAwPQwjTnz4EHH6U7BO5/v2ZSZ5RHyRPidkwPBMJOXUzmzmbTkXPGG3mvXycdxqvIElzQph9iTskwtuC77qVo67ssU24TgkgCOEWqEPpxFh/WuG0cvUABs2vE0TcFHkGqAM= ARC-Message-Signature: i=1; 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Thu, 23 Oct 2025 06:02:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs93-0001H3-4g; Thu, 23 Oct 2025 06:02:09 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs91-00039r-0G; Thu, 23 Oct 2025 06:02:08 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:51 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:51 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 02/13] hw/arm/aspeed: Make aspeed_machine_class_init_cpus_defaults() globally accessible Date: Thu, 23 Oct 2025 18:01:35 +0800 Message-ID: <20251023100150.295370-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213842979154100 Content-Type: text/plain; charset="utf-8" The function aspeed_machine_class_init_cpus_defaults() is now made globally visible so that it can be used by other Aspeed machine C files. Previously, this function was declared as static, restricting its visibility to aspeed.c. Since future machine split files will also need to call this helper to initialize default CPU settings, its declaration has been moved to the common header aspeed.h and the static keyword has been removed. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 383ebb9759..7743ad2fb0 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -59,5 +59,6 @@ struct AspeedMachineClass { bool vbootrom; }; =20 +void aspeed_machine_class_init_cpus_defaults(MachineClass *mc); =20 #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 761b526994..5da21a4d6a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1338,7 +1338,7 @@ static void aspeed_machine_class_props_init(ObjectCla= ss *oc) "Change the SPI Flash model"); } =20 -static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) +void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) { AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(mc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 23 Oct 2025 18:01:52 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:52 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 03/13] hw/arm/aspeed: Make create_pca9552() globally accessible for reuse Date: Thu, 23 Oct 2025 18:01:36 +0800 Message-ID: <20251023100150.295370-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213909541154100 The helper function create_pca9552() is now made globally visible so it can be reused by different Aspeed machine source files. Previously, the function was declared static, limiting its scope to aspeed.c. Since multiple Aspeed machine implementations will require I=C2=B2C device initialization using PCA9552 GPIO expanders, this function has been promoted to global visibility. This change improves code sharing and reduces duplication across machine-specific initialization files. No functional changes. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 7743ad2fb0..d4d63996a6 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -60,5 +60,6 @@ struct AspeedMachineClass { }; =20 void aspeed_machine_class_init_cpus_defaults(MachineClass *mc); +void create_pca9552(AspeedSoCState *soc, int bus_id, int addr); =20 #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 5da21a4d6a..2695f0c11b 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -536,7 +536,7 @@ static void tiogapass_bmc_i2c_init(AspeedMachineState *= bmc) i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x= 4e); } =20 -static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) +void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) { i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), TYPE_PCA9552, addr); --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761213905224225.58912517485692; Thu, 23 Oct 2025 03:05:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9N-0001Mg-5N; Thu, 23 Oct 2025 06:02:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9C-0001I6-Cp; Thu, 23 Oct 2025 06:02:18 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs99-00039r-FE; Thu, 23 Oct 2025 06:02:17 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:52 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:52 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 04/13] hw/arm/aspeed: Make create_pca9554() available for use by other Aspeed machines Date: Thu, 23 Oct 2025 18:01:37 +0800 Message-ID: <20251023100150.295370-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213908239158500 The function create_pca9554() is now made globally accessible so that it can be reused by different Aspeed machine source files. Originally, this helper was declared static inside aspeed.c, restricting its visibility. As future Aspeed machine implementations will also require PCA9554 I=C2=B2C device setup, the function has been exported by removing the static keyword and adding its prototype to aspeed.h. This change promotes better code reuse and consistency across machine initialization code. No functional changes. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index d4d63996a6..fbe684d505 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -61,5 +61,6 @@ struct AspeedMachineClass { =20 void aspeed_machine_class_init_cpus_defaults(MachineClass *mc); void create_pca9552(AspeedSoCState *soc, int bus_id, int addr); +I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr); =20 #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 2695f0c11b..8a22696da9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -542,7 +542,7 @@ void create_pca9552(AspeedSoCState *soc, int bus_id, in= t addr) TYPE_PCA9552, addr); } =20 -static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr) +I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr) { return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), TYPE_PCA9554, addr); --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213906; cv=none; d=zohomail.com; s=zohoarc; b=U77RPNviXq6o7HrtcZnFIiD7pTvl7qY35bGm0fx/2A2v3g84sI3aHO2pgQcrzablWQRQN3duv7RWoxjcnw5bzxLkxTt3QPMHQhfe/n6yo4Jt3/dg9nsp8ran+GY0hmFcLtXTugaaccLu9Z4Bx3EaKQoxZ0Ssxvj9E/3NGzp3b5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213906; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Ps802oJAqSSJPmF4fDvuta40bWd3dq+hMIYi94qhhXM=; b=l1L9Z6elOyDi9y8w9cJ8MK9TMsImo51JjN8h5qm+u1j/rm2CYSMCH8pF4MxzTFDImvLv1qrscpLPCufuGMXHcmE7NFTd64kiWvbDZiG0byexqf+2R0MTCNKDEuzsJe0z8bJXi3Bm62FOhsjrca0YKFAbGXmlRdPrUTuIBC06IfQ= ARC-Authentication-Results: i=1; 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Thu, 23 Oct 2025 18:01:52 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:52 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 05/13] hw/arm/aspeed: Split FP5280G2 machine into a separate source file for maintenance Date: Thu, 23 Oct 2025 18:01:38 +0800 Message-ID: <20251023100150.295370-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213909638154100 Content-Type: text/plain; charset="utf-8" This commit moves the FP5280G2 BMC machine implementation from aspeed.c into a new standalone file aspeed_ast2500_fp5280g2.c. The change improves code organization and prepares the Aspeed machine framework for future expansion and easier maintenance. Key updates include: - Moved fp5280g2_bmc_i2c_init() and related machine class init functions into aspeed_ast2500_fp5280g2.c. - Added new file to hw/arm/meson.build for compilation. - Removed obsolete FP5280G2 definitions from aspeed.c No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 65 ------------------------ hw/arm/aspeed_ast2500_fp5280g2.c | 87 ++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 88 insertions(+), 65 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_fp5280g2.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 8a22696da9..48c3d73e73 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -130,21 +130,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ SCU_AST2500_HW_STRAP_RESERVED1) =20 -/* FP5280G2 hardware value: 0XF100D286 */ -#define FP5280G2_BMC_HW_STRAP1 ( \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_RESERVED28 | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_VGA_CLASS_CODE | \ - SCU_HW_STRAP_LPC_RESET_PIN | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ - SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ - SCU_HW_STRAP_MAC1_RGMII | \ - SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ - SCU_AST2500_HW_STRAP_RESERVED1) - /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 =20 @@ -685,33 +670,6 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc) eeprom_buf); } =20 -static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - I2CSlave *i2c_mux; - - /* The at24c256 */ - at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); - - /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, - 0x48); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, - 0x49); - - i2c_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), - "pca9546", 0x70); - /* It expects a TMP112 but a TMP105 is compatible */ - i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, - 0x4a); - - /* It expects a ds3232 but a ds1338 is good enough */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x= 68); - - /* It expects a pca9555 but a pca9552 is compatible */ - create_pca9552(soc, 8, 0x30); -} - static void rainier_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1607,25 +1565,6 @@ static void aspeed_machine_g220a_class_init(ObjectCl= ass *oc, const void *data) aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Inspur FP5280G2 BMC (ARM1176)"; - mc->deprecation_reason =3D "use 'ast2500-evb' instead"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D FP5280G2_BMC_HW_STRAP1; - amc->fmc_model =3D "n25q512a"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 2; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init =3D fp5280g2_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void = *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2001,10 +1940,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_qcom_firework_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_fp5280g2_class_init, }, { .name =3D MACHINE_TYPE_NAME("quanta-q71l-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_fp5280g2.c b/hw/arm/aspeed_ast2500_fp528= 0g2.c new file mode 100644 index 0000000000..a312c29c5d --- /dev/null +++ b/hw/arm/aspeed_ast2500_fp5280g2.c @@ -0,0 +1,87 @@ +/* + * Inspur FP5280G2 + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" +#include "hw/i2c/i2c_mux_pca954x.h" +#include "hw/sensor/tmp105.h" + +/* FP5280G2 hardware value: 0XF100D286 */ +#define FP5280G2_BMC_HW_STRAP1 ( \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_RESERVED28 | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_LPC_RESET_PIN | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ + SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_MAC1_RGMII | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ + SCU_AST2500_HW_STRAP_RESERVED1) + +static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + I2CSlave *i2c_mux; + + /* The at24c256 */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); + + /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, + 0x49); + + i2c_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), + "pca9546", 0x70); + /* It expects a TMP112 but a TMP105 is compatible */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, + 0x4a); + + /* It expects a ds3232 but a ds1338 is good enough */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x= 68); + + /* It expects a pca9555 but a pca9552 is compatible */ + create_pca9552(soc, 8, 0x30); +} + +static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Inspur FP5280G2 BMC (ARM1176)"; + mc->deprecation_reason =3D "use 'ast2500-evb' instead"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D FP5280G2_BMC_HW_STRAP1; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init =3D fp5280g2_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_fp5280g2_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_fp5280g2_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_fp5280g2_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b88b5b06d7..55513db65b 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', + 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213892; cv=none; d=zohomail.com; s=zohoarc; b=kjweooHt6vZskKx8GZ7g2ecEdhIMvOzVNuM/ktU7BiK67pLJZhuRnE2Ql8LOSsAGS7mCXOtSePCnQcv3qAlcWtQMVAdXWfLQxWt4Krbf/iJWr2eIBzcHcMaOl9pqGFWU5k19Ee9IE9bG2IT9BwcA4RapY3wbl+0D1XNTOfZoiOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213892; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=2h3yHb5iFVfwNVSpqviVI1eGTL2rfpH/IPjPehop6UU=; b=OIF2ATNtweH9V6SfJZbrEmVTQ6WGstK0HpoBhx5P0fMrnFMDIIOXuHcXQ52W97FTRe6GizYjBQjW0J4/qeir8LjmvxwAPXkUymGVj21VEciLSMWUTGGxdKA1c6TYM5s6meIRa4+6aq/SxRxdciowOkHc/iekEvxYubxJji/D5dc= ARC-Authentication-Results: i=1; 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Thu, 23 Oct 2025 18:01:53 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:53 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 06/13] hw/arm/aspeed: Split G220A machine into a separate source file for better maintenance Date: Thu, 23 Oct 2025 18:01:39 +0800 Message-ID: <20251023100150.295370-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213895339154100 Content-Type: text/plain; charset="utf-8" This commit refactors the Bytedance G220A BMC machine by moving its implementation from aspeed.c into a new dedicated file aspeed_ast2500_g220a.c. The goal is to improve modularity and maintainability of Aspeed machine definitions by isolating each platform into its own source file. This aligns with ongoing efforts to simplify aspeed.c, which previously contained all machine configurations. Key updates include: - Moved G220A_BMC_HW_STRAP1 definition and g220a_bmc_i2c_init() function into aspeed_ast2500_g220a.c. - Moved aspeed_machine_g220a_class_init() and related type registration to the new file. - Added the new file to the build system (meson.build). - Removed all G220A-specific code from aspeed.c. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 71 --------------------------- hw/arm/aspeed_ast2500_g220a.c | 91 +++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 92 insertions(+), 71 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_g220a.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 48c3d73e73..dbeb751275 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -116,20 +116,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2500_HW_STRAP_RESERVED1) =20 -#define G220A_BMC_HW_STRAP1 ( \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_RESERVED28 | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_2ND_BOOT_WDT | \ - SCU_HW_STRAP_VGA_CLASS_CODE | \ - SCU_HW_STRAP_LPC_RESET_PIN | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ - SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ - SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ - SCU_AST2500_HW_STRAP_RESERVED1) - /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 =20 @@ -634,42 +620,6 @@ static void witherspoon_bmc_i2c_init(AspeedMachineStat= e *bmc) /* Bus 11: TODO ucd90160@64 */ } =20 -static void g220a_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - DeviceState *dev; - - dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3= ), - "emc1413", 0x4c)); - object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); - - dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1= 2), - "emc1413", 0x4c)); - object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); - - dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1= 3), - "emc1413", 0x4c)); - object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); - object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); - - static uint8_t eeprom_buf[2 * 1024] =3D { - 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, - 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, - 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, - 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, - 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, - 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, - }; - smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, - eeprom_buf); -} - static void rainier_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1548,23 +1498,6 @@ static void aspeed_machine_ast2600_evb_class_init(Ob= jectClass *oc, aspeed_machine_ast2600_class_emmc_init(oc); }; =20 -static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *d= ata) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Bytedance G220A BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D G220A_BMC_HW_STRAP1; - amc->fmc_model =3D "n25q512a"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 2; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init =3D g220a_bmc_i2c_init; - mc->default_ram_size =3D 1024 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void = *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1928,10 +1861,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("tiogapass-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_tiogapass_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("g220a-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_g220a_class_init, }, { .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c new file mode 100644 index 0000000000..d9cc0ca018 --- /dev/null +++ b/hw/arm/aspeed_ast2500_g220a.c @@ -0,0 +1,91 @@ +/* + * Bytedance G220A + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" + +#define G220A_BMC_HW_STRAP1 ( \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_RESERVED28 | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_2ND_BOOT_WDT | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_LPC_RESET_PIN | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ + SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ + SCU_AST2500_HW_STRAP_RESERVED1) + +static void g220a_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + DeviceState *dev; + + dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3= ), + "emc1413", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); + + dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1= 2), + "emc1413", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); + + dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1= 3), + "emc1413", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); + + static uint8_t eeprom_buf[2 * 1024] =3D { + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, + 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, + 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, + 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, + 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, + 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, + }; + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, + eeprom_buf); +} + +static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *d= ata) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Bytedance G220A BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D G220A_BMC_HW_STRAP1; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init =3D g220a_bmc_i2c_init; + mc->default_ram_size =3D 1024 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_g220a_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("g220a-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_g220a_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_g220a_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 55513db65b..a8539ff51e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -45,6 +45,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2500_fp5280g2.c', + 'aspeed_ast2500_g220a.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761213902179415.20259176815193; Thu, 23 Oct 2025 03:05:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9R-0001Oe-Lq; Thu, 23 Oct 2025 06:02:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9P-0001Nt-L0; Thu, 23 Oct 2025 06:02:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9L-00039r-S2; Thu, 23 Oct 2025 06:02:31 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:53 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:53 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 07/13] hw/arm/aspeed: Split Tiogapass machine into a separate source file for cleanup Date: Thu, 23 Oct 2025 18:01:40 +0800 Message-ID: <20251023100150.295370-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213906327158500 Content-Type: text/plain; charset="utf-8" This commit moves the Tiogapass BMC machine implementation out of aspeed.c into a new dedicated file aspeed_ast2500_tiogapass.c. To support splitting Tiogapass into a dedicated source file, a new TIOGAPASS_BMC_HW_STRAP1 macro is added as a copy of AST2500_EVB_HW_STRAP1. The change follows the ongoing effort to modularize Aspeed platform support by splitting each machine definition into its own source file. This makes aspeed.c cleaner, easier to maintain, and simplifies future feature additions or refactoring for individual machines. Key updates include: - Removed tiogapass_bmc_i2c_init() and its FRU data from aspeed.c and aspeed_eeprom.c. - Removed Tiogapass type registration from aspeed_machine_types[]. - Added new source file aspeed_ast2500_tiogapass.c to meson.build. - Removed unused Tiogapass FRUID declarations from aspeed_eeprom.h. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_eeprom.h | 4 -- hw/arm/aspeed.c | 35 ------------ hw/arm/aspeed_ast2500_tiogapass.c | 89 +++++++++++++++++++++++++++++++ hw/arm/aspeed_eeprom.c | 22 -------- hw/arm/meson.build | 1 + 5 files changed, 90 insertions(+), 61 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_tiogapass.c diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index 3ed9bc1d9a..a9ae95940c 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -7,10 +7,6 @@ #ifndef ASPEED_EEPROM_H #define ASPEED_EEPROM_H =20 - -extern const uint8_t tiogapass_bmc_fruid[]; -extern const size_t tiogapass_bmc_fruid_len; - extern const uint8_t fby35_nic_fruid[]; extern const uint8_t fby35_bb_fruid[]; extern const uint8_t fby35_bmc_fruid[]; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index dbeb751275..4ac998df4e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -494,19 +494,6 @@ static void romulus_bmc_i2c_init(AspeedMachineState *b= mc) i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); } =20 -static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - - at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); - at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * Ki= B, - tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); - /* TMP421 */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x= 1f); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x= 4f); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x= 4e); -} - void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) { i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), @@ -1423,24 +1410,6 @@ static void aspeed_machine_romulus_class_init(Object= Class *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Facebook Tiogapass BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D AST2500_EVB_HW_STRAP1; - amc->hw_strap2 =3D 0; - amc->fmc_model =3D "n25q256a"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 2; - amc->i2c_init =3D tiogapass_bmc_i2c_init; - mc->default_ram_size =3D 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, const void *data) { @@ -1857,10 +1826,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("yosemitev2-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_yosemitev2_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("tiogapass-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_tiogapass_class_init, }, { .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiog= apass.c new file mode 100644 index 0000000000..3fd81eb5be --- /dev/null +++ b/hw/arm/aspeed_ast2500_tiogapass.c @@ -0,0 +1,89 @@ +/* + * Facebook Tiogapass + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" + +/* value: 0xF100C2E6 */ +#define TIOGAPASS_BMC_HW_STRAP1 (( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_MAC1_RGMII | \ + SCU_HW_STRAP_MAC0_RGMII) & \ + ~SCU_HW_STRAP_2ND_BOOT_WDT) + +/* Tiogapass BMC FRU */ +static const uint8_t tiogapass_bmc_fruid[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36, + 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d, + 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f, + 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, + 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x54, 0x69, 0x6f, 0x67, 0x61, + 0x20, 0x50, 0x61, 0x73, 0x73, 0x20, 0x53, 0x69, 0x6e, 0x67, 0x6c, 0x65, + 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0xc4, 0x58, 0x58, 0x58, 0x32, 0xcd, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f, + 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, +}; + +static const size_t tiogapass_bmc_fruid_len =3D sizeof(tiogapass_bmc_fruid= ); + +static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * Ki= B, + tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); + /* TMP421 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x= 1f); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x= 4f); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x= 4e); +} + +static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Facebook Tiogapass BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D TIOGAPASS_BMC_HW_STRAP1; + amc->hw_strap2 =3D 0; + amc->fmc_model =3D "n25q256a"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 2; + amc->i2c_init =3D tiogapass_bmc_i2c_init; + mc->default_ram_size =3D 1 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_tiogapass_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("tiogapass-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_tiogapass_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_tiogapass_types) + diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index 8bbbdec834..f0ced29cf1 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -7,27 +7,6 @@ #include "qemu/osdep.h" #include "aspeed_eeprom.h" =20 -/* Tiogapass BMC FRU */ -const uint8_t tiogapass_bmc_fruid[] =3D { - 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36, - 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d, - 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f, - 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, - 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x54, 0x69, 0x6f, 0x67, 0x61, - 0x20, 0x50, 0x61, 0x73, 0x73, 0x20, 0x53, 0x69, 0x6e, 0x67, 0x6c, 0x65, - 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0xc4, 0x58, 0x58, 0x58, 0x32, 0xcd, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f, - 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, -}; - const uint8_t fby35_nic_fruid[] =3D { 0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7, 0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd, @@ -181,7 +160,6 @@ const uint8_t gb200nvl_bmc_fruid[] =3D { =20 }; =20 -const size_t tiogapass_bmc_fruid_len =3D sizeof(tiogapass_bmc_fruid); const size_t fby35_nic_fruid_len =3D sizeof(fby35_nic_fruid); const size_t fby35_bb_fruid_len =3D sizeof(fby35_bb_fruid); const size_t fby35_bmc_fruid_len =3D sizeof(fby35_bmc_fruid); diff --git a/hw/arm/meson.build b/hw/arm/meson.build index a8539ff51e..849534f6ad 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -46,6 +46,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2400.c', 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', + 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 23 Oct 2025 18:01:54 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 08/13] hw/arm/aspeed: Split YosemiteV2 machine into a separate source file for maintainability Date: Thu, 23 Oct 2025 18:01:41 +0800 Message-ID: <20251023100150.295370-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213843095154100 Content-Type: text/plain; charset="utf-8" This commit moves the YosemiteV2 BMC machine implementation from aspeed.c into a new standalone file aspeed_ast2500_yosemitev2.c. To support splitting YosemiteV2 into a dedicated source file, a new YOSEMITEV2_BMC_HW_STRAP1 macro is added as a copy of AST2500_EVB_HW_STRAP1. The refactor is part of an ongoing effort to modularize Aspeed machine definitions by separating each board into its own source file. This improves code readability, maintainability, and simplifies future platform-specific changes. Key updates include: - Moved yosemitev2_bmc_i2c_init() and its FRU data into a new file. - Removed aspeed_machine_yosemitev2_class_init() and type registration from aspeed.c. - Removed YosemiteV2 FRUID data and declarations from aspeed_eeprom.c and aspeed_eeprom.h. - Added aspeed_ast2500_yosemitev2.c to the build system (meson.build). No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_eeprom.h | 3 - hw/arm/aspeed.c | 36 ------------ hw/arm/aspeed_ast2500_yosemitev2.c | 90 ++++++++++++++++++++++++++++++ hw/arm/aspeed_eeprom.c | 22 -------- hw/arm/meson.build | 1 + 5 files changed, 91 insertions(+), 61 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_yosemitev2.c diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index a9ae95940c..5448eeeab7 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -14,9 +14,6 @@ extern const size_t fby35_nic_fruid_len; extern const size_t fby35_bb_fruid_len; extern const size_t fby35_bmc_fruid_len; =20 -extern const uint8_t yosemitev2_bmc_fruid[]; -extern const size_t yosemitev2_bmc_fruid_len; - extern const uint8_t rainier_bb_fruid[]; extern const size_t rainier_bb_fruid_len; extern const uint8_t rainier_bmc_fruid[]; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4ac998df4e..f890d30d0e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -469,20 +469,6 @@ static void ast2600_evb_i2c_init(AspeedMachineState *b= mc) TYPE_TMP105, 0x4d); } =20 -static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - - at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); - at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * Ki= B, - yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); - /* TMP421 */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0= x1f); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x= 4e); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x= 4f); - -} - static void romulus_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1375,24 +1361,6 @@ static void aspeed_machine_ast2500_evb_class_init(Ob= jectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Facebook YosemiteV2 BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D AST2500_EVB_HW_STRAP1; - amc->hw_strap2 =3D 0; - amc->fmc_model =3D "n25q256a"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 2; - amc->i2c_init =3D yosemitev2_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_romulus_class_init(ObjectClass *oc, const void *data) { @@ -1822,10 +1790,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("ast2600-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_ast2600_evb_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("yosemitev2-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_yosemitev2_class_init, }, { .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yos= emitev2.c new file mode 100644 index 0000000000..4ec9beb2b7 --- /dev/null +++ b/hw/arm/aspeed_ast2500_yosemitev2.c @@ -0,0 +1,90 @@ +/* + * Facebook YosemiteV2 + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" + +/* value: 0xF100C2E6 */ +#define YOSEMITEV2_BMC_HW_STRAP1 (( = \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_MAC1_RGMII | \ + SCU_HW_STRAP_MAC0_RGMII) & \ + ~SCU_HW_STRAP_2ND_BOOT_WDT) + +/* Yosemite V2 BMC FRU */ +static const uint8_t yosemitev2_bmc_fruid[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36, + 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x61, + 0x73, 0x65, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x4d, 0x50, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, + 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d, + 0x69, 0x74, 0x65, 0x20, 0x56, 0x32, 0x20, 0x4d, 0x50, 0x00, 0x00, 0x00, + 0x00, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, + 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f, + 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, +}; + +static const size_t yosemitev2_bmc_fruid_len =3D sizeof(yosemitev2_bmc_fru= id); + +static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * Ki= B, + yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); + /* TMP421 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0= x1f); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x= 4e); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x= 4f); + +} + +static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Facebook YosemiteV2 BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D YOSEMITEV2_BMC_HW_STRAP1; + amc->hw_strap2 =3D 0; + amc->fmc_model =3D "n25q256a"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 2; + amc->i2c_init =3D yosemitev2_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_yosemitev2_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("yosemitev2-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_yosemitev2_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_yosemitev2_types) + diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index f0ced29cf1..124277eaca 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -78,27 +78,6 @@ const uint8_t fby35_bmc_fruid[] =3D { 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, }; =20 -/* Yosemite V2 BMC FRU */ -const uint8_t yosemitev2_bmc_fruid[] =3D { - 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36, - 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x61, - 0x73, 0x65, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x4d, 0x50, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, - 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d, - 0x69, 0x74, 0x65, 0x20, 0x56, 0x32, 0x20, 0x4d, 0x50, 0x00, 0x00, 0x00, - 0x00, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, - 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f, - 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, -}; - const uint8_t rainier_bb_fruid[] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02, @@ -163,7 +142,6 @@ const uint8_t gb200nvl_bmc_fruid[] =3D { const size_t fby35_nic_fruid_len =3D sizeof(fby35_nic_fruid); const size_t fby35_bb_fruid_len =3D sizeof(fby35_bb_fruid); const size_t fby35_bmc_fruid_len =3D sizeof(fby35_bmc_fruid); -const size_t yosemitev2_bmc_fruid_len =3D sizeof(yosemitev2_bmc_fruid); const size_t rainier_bb_fruid_len =3D sizeof(rainier_bb_fruid); const size_t rainier_bmc_fruid_len =3D sizeof(rainier_bmc_fruid); const size_t gb200nvl_bmc_fruid_len =3D sizeof(gb200nvl_bmc_fruid); diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 849534f6ad..d07ebc9dd7 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -47,6 +47,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_tiogapass.c', + 'aspeed_ast2500_yosemitev2.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213849; cv=none; d=zohomail.com; s=zohoarc; b=RbkXZcBcJ/jLQtPynpO91lZlJQrw1GiaS+D3xcVs8PPV5UouJLi9eqaZgOA4ZbO84P9U+GntV8JZh+FlkmxJkt82QwN+Gb+ORyF+XSqTNmv0uoyINbGZR4++hOGzRI2cMn8F7ekzXnlhnwIwblEXPafbZLSM8Q0mEWD1Wg5rVsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213849; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=GTEeQuViup08Dy9t/EMp9Q+L8d0558O68R70nXDRSEs=; b=bDwLjuhD246nDvn/tmi/2qzPwTFhZ0pTxdluq0ptGhYYyf9qcmwRNeMApMhAIrfPYOUGeDl8S7USu03Z8Q9SF50MKnWYmsc2HFtvMSjK301k3SD/CqE4hBngg4ruUi6c6JT5sClXb16jqW+VKxxja54J2x1VDdw8Ul6+VN9WutE= ARC-Authentication-Results: i=1; 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Thu, 23 Oct 2025 18:01:54 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 09/13] hw/arm/aspeed: Split Witherspoon machine into a separate source file for maintainability Date: Thu, 23 Oct 2025 18:01:42 +0800 Message-ID: <20251023100150.295370-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213851177154100 Content-Type: text/plain; charset="utf-8" This commit moves the Witherspoon BMC machine implementation out of aspeed.c and into a new dedicated file aspeed_ast2500_witherspoon.c. To support splitting Witherspoon into a dedicated source file, a new WITHERSPOON_BMC_HW_STRAP1 macro is added as a copy of ROMULUS_BMC_HW_STRAP1. The change is part of a broader effort to modularize Aspeed board definitions, allowing each machine type to be maintained and updated independently. By isolating Witherspoon logic, the aspeed.c file becomes cleaner and easier to manage as more platforms are added. Key updates include: - Moved witherspoon_bmc_i2c_init() and related LED setup code into aspeed_ast2500_witherspoon.c. - Added WITHERSPOON_BMC_HW_STRAP1 replacement macro for local use. - Removed aspeed_machine_witherspoon_class_init() and type registration from aspeed.c. - Added the new file to meson.build for compilation. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 81 -------------------- hw/arm/aspeed_ast2500_witherspoon.c | 111 ++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 112 insertions(+), 81 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_witherspoon.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index f890d30d0e..91d59e0d2d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -116,9 +116,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2500_HW_STRAP_RESERVED1) =20 -/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ -#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 - /* Quanta-Q71l hardware value */ #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ @@ -536,63 +533,6 @@ static void sonorapass_bmc_i2c_init(AspeedMachineState= *bmc) =20 } =20 -static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) -{ - static const struct { - unsigned gpio_id; - LEDColor color; - const char *description; - bool gpio_polarity; - } pca1_leds[] =3D { - {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, - {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, - {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, - }; - AspeedSoCState *soc =3D bmc->soc; - uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); - DeviceState *dev; - LEDState *led; - - /* Bus 3: TODO bmp280@77 */ - dev =3D DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); - qdev_prop_set_string(dev, "description", "pca1"); - i2c_slave_realize_and_unref(I2C_SLAVE(dev), - aspeed_i2c_get_bus(&soc->i2c, 3), - &error_fatal); - - for (size_t i =3D 0; i < ARRAY_SIZE(pca1_leds); i++) { - led =3D led_create_simple(OBJECT(bmc), - pca1_leds[i].gpio_polarity, - pca1_leds[i].color, - pca1_leds[i].description); - qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, - qdev_get_gpio_in(DEVICE(led), 0)); - } - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x= 76); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", = 0x52); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x= 4c); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x= 4c); - - /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, - 0x4a); - - /* - * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is - * good enough - */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); - - smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, - eeprom_buf); - dev =3D DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); - qdev_prop_set_string(dev, "description", "pca0"); - i2c_slave_realize_and_unref(I2C_SLAVE(dev), - aspeed_i2c_get_bus(&soc->i2c, 11), - &error_fatal); - /* Bus 11: TODO ucd90160@64 */ -} - static void rainier_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1396,23 +1336,6 @@ static void aspeed_machine_sonorapass_class_init(Obj= ectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "OpenPOWER Witherspoon BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D WITHERSPOON_BMC_HW_STRAP1; - amc->fmc_model =3D "mx25l25635f"; - amc->spi_model =3D "mx66l1g45g"; - amc->num_cs =3D 2; - amc->i2c_init =3D witherspoon_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, const void *data) { @@ -1782,10 +1705,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("sonorapass-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_sonorapass_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("witherspoon-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_witherspoon_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast2600-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_wi= therspoon.c new file mode 100644 index 0000000000..249d63a9dd --- /dev/null +++ b/hw/arm/aspeed_ast2500_witherspoon.c @@ -0,0 +1,111 @@ +/* + * OpenPOWER Witherspoon + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/misc/led.h" +#include "hw/sensor/tmp105.h" +#include "hw/i2c/smbus_eeprom.h" +#include "hw/gpio/pca9552.h" + +/* Witherspoon hardware value: 0xF10AD216 */ +#define WITHERSPOON_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) + +static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) +{ + static const struct { + unsigned gpio_id; + LEDColor color; + const char *description; + bool gpio_polarity; + } pca1_leds[] =3D { + {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, + {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, + {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, + }; + AspeedSoCState *soc =3D bmc->soc; + uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); + DeviceState *dev; + LEDState *led; + + /* Bus 3: TODO bmp280@77 */ + dev =3D DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); + qdev_prop_set_string(dev, "description", "pca1"); + i2c_slave_realize_and_unref(I2C_SLAVE(dev), + aspeed_i2c_get_bus(&soc->i2c, 3), + &error_fatal); + + for (size_t i =3D 0; i < ARRAY_SIZE(pca1_leds); i++) { + led =3D led_create_simple(OBJECT(bmc), + pca1_leds[i].gpio_polarity, + pca1_leds[i].color, + pca1_leds[i].description); + qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, + qdev_get_gpio_in(DEVICE(led), 0)); + } + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x= 76); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", = 0x52); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x= 4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x= 4c); + + /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, + 0x4a); + + /* + * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is + * good enough + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, + eeprom_buf); + dev =3D DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); + qdev_prop_set_string(dev, "description", "pca0"); + i2c_slave_realize_and_unref(I2C_SLAVE(dev), + aspeed_i2c_get_bus(&soc->i2c, 11), + &error_fatal); + /* Bus 11: TODO ucd90160@64 */ +} + +static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "OpenPOWER Witherspoon BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D WITHERSPOON_BMC_HW_STRAP1; + amc->fmc_model =3D "mx25l25635f"; + amc->spi_model =3D "mx66l1g45g"; + amc->num_cs =3D 2; + amc->i2c_init =3D witherspoon_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_witherspoon_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("witherspoon-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_witherspoon_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_witherspoon_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index d07ebc9dd7..d3726d1b9d 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -47,6 +47,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_tiogapass.c', + 'aspeed_ast2500_witherspoon.c', 'aspeed_ast2500_yosemitev2.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213875; cv=none; d=zohomail.com; s=zohoarc; b=kWVHIUYLPzmZsEl3xiyCVmJioHkDjbaZtCJ2nJB8f7QXndk2qoMMBsRrFAtdDL+WArYi6sFX8Icowtp2FTWX1yWRw/tz8gLtu/zBPhTjuGWlUAz7rdp/qWayle/zQx0yK+VW8FYjFIkYuNf1zLxqSBCgyTs09gAqbbTFMiFurjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213875; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ag798dWDbhlFQzdsExY4Sl1T9EdlNvQyD+9l2Uoyqwg=; b=IpUVhW2tK6kYNV2ajx+PZHzzrvdLNDsGl469+Y6TB5hQQvOf0QTI4xxM9zuGpGnp0nNamNQgjbwuBuLUJLH30aaAA4dxaxD2prdGeu+0jcTCOSQXRDE3bu4wJW4mn5s0UtaVpLn8ipQy8Qi9R7aHZiTiMsYuI4vnY5etPASPyCU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176121387509764.23712846894784; Thu, 23 Oct 2025 03:04:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9c-0001Rz-HN; Thu, 23 Oct 2025 06:02:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9b-0001RY-2X; Thu, 23 Oct 2025 06:02:43 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9Y-0003D7-Sj; Thu, 23 Oct 2025 06:02:42 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:54 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 10/13] hw/arm/aspeed: Split Sonorapass machine into a separate source file for maintainability Date: Thu, 23 Oct 2025 18:01:43 +0800 Message-ID: <20251023100150.295370-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213877821158500 This commit moves the Sonorapass BMC machine implementation out of aspeed.c and into a new standalone file aspeed_ast2500_sonorapass.c. The refactor continues the effort to modularize Aspeed platform support by separating each board=E2=80=99s implementation into its own source file. This improves maintainability, readability, and simplifies future updates to individual machine configurations. Key updates include: - Moved SONORAPASS_BMC_HW_STRAP1 definition into the new file. - Moved sonorapass_bmc_i2c_init() and all I=C2=B2C device initialization logic from aspeed.c into aspeed_ast2500_sonorapass.c. - Moved aspeed_machine_sonorapass_class_init() and type registration into the new file. - Added the new file to the build system (meson.build). - Removed all Sonorapass-specific code and definitions from aspeed.c No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 81 ----------------------- hw/arm/aspeed_ast2500_sonorapass.c | 101 +++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 102 insertions(+), 81 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_sonorapass.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 91d59e0d2d..f01d71db8f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -101,21 +101,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) =20 -/* Sonorapass hardware value: 0xF100D216 */ -#define SONORAPASS_BMC_HW_STRAP1 ( \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_RESERVED28 | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_VGA_CLASS_CODE | \ - SCU_HW_STRAP_LPC_RESET_PIN | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ - SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ - SCU_HW_STRAP_VGA_BIOS_ROM | \ - SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ - SCU_AST2500_HW_STRAP_RESERVED1) - /* Quanta-Q71l hardware value */ #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ @@ -489,50 +474,6 @@ I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_= id, int addr) TYPE_PCA9554, addr); } =20 -static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - - /* bus 2 : */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x= 48); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x= 49); - /* bus 2 : pca9546 @ 0x73 */ - - /* bus 3 : pca9548 @ 0x70 */ - - /* bus 4 : */ - uint8_t *eeprom4_54 =3D g_malloc0(8 * 1024); - smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, - eeprom4_54); - /* PCA9539 @ 0x76, but PCA9552 is compatible */ - create_pca9552(soc, 4, 0x76); - /* PCA9539 @ 0x77, but PCA9552 is compatible */ - create_pca9552(soc, 4, 0x77); - - /* bus 6 : */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x= 48); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x= 49); - /* bus 6 : pca9546 @ 0x73 */ - - /* bus 8 : */ - uint8_t *eeprom8_56 =3D g_malloc0(8 * 1024); - smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, - eeprom8_56); - create_pca9552(soc, 8, 0x60); - create_pca9552(soc, 8, 0x61); - /* bus 8 : adc128d818 @ 0x1d */ - /* bus 8 : adc128d818 @ 0x1f */ - - /* - * bus 13 : pca9548 @ 0x71 - * - channel 3: - * - tmm421 @ 0x4c - * - tmp421 @ 0x4e - * - tmp421 @ 0x4f - */ - -} - static void rainier_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1318,24 +1259,6 @@ static void aspeed_machine_romulus_class_init(Object= Class *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "OCP SonoraPass BMC (ARM1176)"; - mc->deprecation_reason =3D "use 'ast2500-evb' instead"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D SONORAPASS_BMC_HW_STRAP1; - amc->fmc_model =3D "mx66l1g45g"; - amc->spi_model =3D "mx66l1g45g"; - amc->num_cs =3D 2; - amc->i2c_init =3D sonorapass_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, const void *data) { @@ -1701,10 +1624,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("romulus-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_romulus_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("sonorapass-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_sonorapass_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast2600-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_sonorapass.c b/hw/arm/aspeed_ast2500_son= orapass.c new file mode 100644 index 0000000000..6c7f2da5cc --- /dev/null +++ b/hw/arm/aspeed_ast2500_sonorapass.c @@ -0,0 +1,101 @@ +/* + * OCP SonoraPass + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" + +/* Sonorapass hardware value: 0xF100D216 */ +#define SONORAPASS_BMC_HW_STRAP1 ( \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_RESERVED28 | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_LPC_RESET_PIN | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ + SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_VGA_BIOS_ROM | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ + SCU_AST2500_HW_STRAP_RESERVED1) + +static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + /* bus 2 : */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x= 48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x= 49); + /* bus 2 : pca9546 @ 0x73 */ + + /* bus 3 : pca9548 @ 0x70 */ + + /* bus 4 : */ + uint8_t *eeprom4_54 =3D g_malloc0(8 * 1024); + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, + eeprom4_54); + /* PCA9539 @ 0x76, but PCA9552 is compatible */ + create_pca9552(soc, 4, 0x76); + /* PCA9539 @ 0x77, but PCA9552 is compatible */ + create_pca9552(soc, 4, 0x77); + + /* bus 6 : */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x= 48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x= 49); + /* bus 6 : pca9546 @ 0x73 */ + + /* bus 8 : */ + uint8_t *eeprom8_56 =3D g_malloc0(8 * 1024); + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, + eeprom8_56); + create_pca9552(soc, 8, 0x60); + create_pca9552(soc, 8, 0x61); + /* bus 8 : adc128d818 @ 0x1d */ + /* bus 8 : adc128d818 @ 0x1f */ + + /* + * bus 13 : pca9548 @ 0x71 + * - channel 3: + * - tmm421 @ 0x4c + * - tmp421 @ 0x4e + * - tmp421 @ 0x4f + */ + +} + +static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "OCP SonoraPass BMC (ARM1176)"; + mc->deprecation_reason =3D "use 'ast2500-evb' instead"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D SONORAPASS_BMC_HW_STRAP1; + amc->fmc_model =3D "mx66l1g45g"; + amc->spi_model =3D "mx66l1g45g"; + amc->num_cs =3D 2; + amc->i2c_init =3D sonorapass_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_sonorapass_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("sonorapass-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_sonorapass_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_sonorapass_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index d3726d1b9d..94f8a82f17 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -46,6 +46,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2400.c', 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', + 'aspeed_ast2500_sonorapass.c', 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2500_witherspoon.c', 'aspeed_ast2500_yosemitev2.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213806; cv=none; d=zohomail.com; s=zohoarc; b=fBVyjUvNjvIidpWctV6v2qUrdkcR6Edt4MQ6+a2fmU2055QSBweeU2PiPVtzq6qM7fU4xLhMIUruE7xMywl2h2szuWvkZUnRkrfRewkrZ8xUEOROaVhytab0XdBwtlNIEXqCahc5mOEQ0bHvDaMuTSlWBpA5oyaPnOwBr7yf43w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213806; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=CIFPuspYPov4RkBwhH+dxxbZ55fasnGvaPB/JDpbjDk=; b=naO4dcM2yl5xIl7pCfoHGc6pn68d7g/RISgXfP4qDYiXvU3KdJ8vAZ5XyD04gy58eLeuZ8Oiy41i70xhFXoB0xiplf3ac7KWKdFEaNO59kgcl4bGp1nCucB8sMq70HH3zHn2F++x2u13Ig+BZZtl38qEwbxh43wQ6N9p2Q9m+lM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1761213806224142.60015988548014; Thu, 23 Oct 2025 03:03:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9g-0001Wc-8K; Thu, 23 Oct 2025 06:02:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9d-0001UI-TS; Thu, 23 Oct 2025 06:02:46 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9b-0003D7-Th; Thu, 23 Oct 2025 06:02:45 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 11/13] hw/arm/aspeed: Split Romulus machine into a separate source file for maintainability Date: Thu, 23 Oct 2025 18:01:44 +0800 Message-ID: <20251023100150.295370-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213809346158500 This commit moves the Romulus BMC machine implementation out of aspeed.c into a new standalone file aspeed_ast2500_romulus.c. The refactor continues the modularization of Aspeed platform definitions, separating each board into its own C source file to improve maintainability, readability, and reduce code clutter in aspeed.c. Key updates include: - Moved ROMULUS_BMC_HW_STRAP1 definition to the new file. - Moved romulus_bmc_i2c_init() and related I=C2=B2C device setup. - Moved aspeed_machine_romulus_class_init() and type registration to aspeed_ast2500_romulus.c. - Added the new file to the build system (meson.build). - Removed all Romulus-specific code from aspeed.c. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 42 ----------------------- hw/arm/aspeed_ast2500_romulus.c | 61 +++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 62 insertions(+), 42 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_romulus.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index f01d71db8f..a97d037acb 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -91,16 +91,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_MAC0_RGMII) & \ ~SCU_HW_STRAP_2ND_BOOT_WDT) =20 -/* Romulus hardware value: 0xF10AD206 */ -#define ROMULUS_BMC_HW_STRAP1 ( \ - AST2500_HW_STRAP1_DEFAULTS | \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) - /* Quanta-Q71l hardware value */ #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ @@ -451,17 +441,6 @@ static void ast2600_evb_i2c_init(AspeedMachineState *b= mc) TYPE_TMP105, 0x4d); } =20 -static void romulus_bmc_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - - /* - * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is - * good enough - */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); -} - void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) { i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), @@ -1242,23 +1221,6 @@ static void aspeed_machine_ast2500_evb_class_init(Ob= jectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); }; =20 -static void aspeed_machine_romulus_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "OpenPOWER Romulus BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D ROMULUS_BMC_HW_STRAP1; - amc->fmc_model =3D "n25q256a"; - amc->spi_model =3D "mx66l1g45g"; - amc->num_cs =3D 2; - amc->i2c_init =3D romulus_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, const void *data) { @@ -1620,10 +1582,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("ast2500-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_ast2500_evb_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("romulus-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_romulus_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast2600-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulu= s.c new file mode 100644 index 0000000000..6902319e37 --- /dev/null +++ b/hw/arm/aspeed_ast2500_romulus.c @@ -0,0 +1,61 @@ +/* + * OpenPOWER Romulus + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" + +/* Romulus hardware value: 0xF10AD206 */ +#define ROMULUS_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) + +static void romulus_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + /* + * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is + * good enough + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); +} + +static void aspeed_machine_romulus_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "OpenPOWER Romulus BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D ROMULUS_BMC_HW_STRAP1; + amc->fmc_model =3D "n25q256a"; + amc->spi_model =3D "mx66l1g45g"; + amc->num_cs =3D 2; + amc->i2c_init =3D romulus_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_romulus_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("romulus-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_romulus_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_romulus_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 94f8a82f17..fdb825fd0e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -46,6 +46,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2400.c', 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', + 'aspeed_ast2500_romulus.c', 'aspeed_ast2500_sonorapass.c', 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2500_witherspoon.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 23 Oct 2025 18:01:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 12/13] hw/arm/aspeed: Split Supermicro X11SPI machine into a separate file for maintainability Date: Thu, 23 Oct 2025 18:01:45 +0800 Message-ID: <20251023100150.295370-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213829802158500 This commit moves the Supermicro X11SPI BMC machine definition from aspeed.c into a new standalone file aspeed_ast2500_supermicro-x11spi.c, and adds a dedicated I=C2=B2C initialization function for the platform. The refactor continues the effort to modularize Aspeed platform support, ensuring each machine model is defined in its own source file. This improves code organization, readability, and simplifies maintenance when adding or modifying platform-specific behavior. Previously, the Supermicro X11SPI machine reused palmetto_bmc_i2c_init() for its I=C2=B2C setup. To make the machine definition fully self-contained, the function was copied and renamed to supermicro_x11spi_bmc_i2c_init(). This ensures that the machine can evolve independently without depending on Palmetto=E2=80=99s board logi Key updates include: - Moved SUPERMICRO_X11SPI_BMC_HW_STRAP1 macro and machine class init (aspeed_machine_supermicro_x11spi_bmc_class_init) into a new file. - Added new function supermicro_x11spi_bmc_i2c_init() copied from palmetto_bmc_i2c_init() for independent control. - Updated the machine definition to use the new I=C2=B2C init function. - Registered the new source file in meson.build. - Removed all Supermicro X11SPI-related definitions from aspeed.c. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 32 ---------- hw/arm/aspeed_ast2500_supermicro-x11spi.c | 76 +++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 77 insertions(+), 32 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_supermicro-x11spi.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a97d037acb..3618f01ea2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -70,16 +70,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) =20 -/* TODO: Find the actual hardware value */ -#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ - AST2500_HW_STRAP1_DEFAULTS | \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_SPI_WIDTH | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) - /* AST2500 evb hardware value: 0xF100C2E6 */ #define AST2500_EVB_HW_STRAP1 (( \ AST2500_HW_STRAP1_DEFAULTS | \ @@ -1186,24 +1176,6 @@ static void aspeed_machine_supermicrox11_bmc_class_i= nit(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } =20 -static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, - const void *da= ta) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Supermicro X11 SPI BMC (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D SUPERMICRO_X11SPI_BMC_HW_STRAP1; - amc->fmc_model =3D "mx25l25635e"; - amc->spi_model =3D "mx25l25635e"; - amc->num_cs =3D 1; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init =3D palmetto_bmc_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, const void *data) { @@ -1574,10 +1546,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_supermicrox11_bmc_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_supermicro_x11spi_bmc_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast2500-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2= 500_supermicro-x11spi.c new file mode 100644 index 0000000000..49332463c4 --- /dev/null +++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c @@ -0,0 +1,76 @@ +/* + * Supermicro X11 SPI + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" + +/* TODO: Find the actual hardware value */ +#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) + +static void supermicro_x11spi_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + DeviceState *dev; + uint8_t *eeprom_buf =3D g_malloc0(32 * 1024); + + /* + * The palmetto platform expects a ds3231 RTC but a ds1338 is + * enough to provide basic RTC features. Alarms will be missing + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x= 68); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, + eeprom_buf); + + /* add a TMP423 temperature sensor */ + dev =3D DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2= ), + "tmp423", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abo= rt); + object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_ab= ort); +} + +static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *o= c, + const void *da= ta) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Supermicro X11 SPI BMC (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D SUPERMICRO_X11SPI_BMC_HW_STRAP1; + amc->fmc_model =3D "mx25l25635e"; + amc->spi_model =3D "mx25l25635e"; + amc->num_cs =3D 1; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init =3D supermicro_x11spi_bmc_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast2500_supermicro_x11spi_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_supermicro_x11spi_bmc_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_supermicro_x11spi_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index fdb825fd0e..f788baabeb 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -48,6 +48,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_romulus.c', 'aspeed_ast2500_sonorapass.c', + 'aspeed_ast2500_supermicro-x11spi.c', 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2500_witherspoon.c', 'aspeed_ast2500_yosemitev2.c', --=20 2.43.0 From nobody Fri Nov 14 18:19:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1761213831; cv=none; d=zohomail.com; s=zohoarc; b=Rg5J3kstA6RAO+VRy/zQAJqSP/iME/qfYsy4jw+uI9YD5FUwgvFuVuZS+lF5fQ9Q1y/jXjNsBh7pihpFQluQXFqyBiib9kMLirVKLdMGHF9YqB4AUsBiarzLbqhDTK/TLt7zGNedpDczPL2mbPDyIPG3I4JbohB7XCEk2fHVOrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761213831; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=/0X9jcKVOMTGtA+P2OExAm+PSxIclLVlIJvKPS03Hj0=; b=Mku1PVU8ckkSZ6fY79a14UH+oyYWgB2IRV8yDIyVREy8HHtx0WsLKiGRyeAo2t4Gxp8b4+ahPuczMq/NeGmxO8imTarRfpIV7fXtV9974S2SMAl2ZcfacUU9o9PlKu1VEcx6Qxfv2kL4CBhjwnHETPdC0tCTWOss3VW6FxWZaIo= ARC-Authentication-Results: i=1; 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Thu, 23 Oct 2025 18:01:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 13/13] hw/arm/aspeed: Split AST2500 EVB machine into a separate source file for maintainability Date: Thu, 23 Oct 2025 18:01:46 +0800 Message-ID: <20251023100150.295370-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1761213834706154100 This commit moves the AST2500 EVB machine implementation out of aspeed.c into a new standalone file aspeed_ast2500_evb.c. This refactor continues the modularization effort for Aspeed platform support, placing each board=E2=80=99s logic in its own dedicated source fil= e. It improves maintainability, readability, and simplifies future development for new platforms without cluttering aspeed.c. Key updates include: - Moved AST2500_EVB_HW_STRAP1 macro definition into the new file. - Moved ast2500_evb_i2c_init() I=C2=B2C initialization logic. - Moved aspeed_machine_ast2500_evb_class_init() and type registration. - Added aspeed_ast2500_evb.c to the build system (meson.build). - Removed all AST2500 EVB=E2=80=93specific code and macros from aspeed.c. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 45 ------------------------- hw/arm/aspeed_ast2500_evb.c | 66 +++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 67 insertions(+), 45 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_evb.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 3618f01ea2..11c74c3e1b 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -70,17 +70,6 @@ static struct arm_boot_info aspeed_board_binfo =3D { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) =20 -/* AST2500 evb hardware value: 0xF100C2E6 */ -#define AST2500_EVB_HW_STRAP1 (( \ - AST2500_HW_STRAP1_DEFAULTS | \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_MAC1_RGMII | \ - SCU_HW_STRAP_MAC0_RGMII) & \ - ~SCU_HW_STRAP_2ND_BOOT_WDT) - /* Quanta-Q71l hardware value */ #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ @@ -405,19 +394,6 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineStat= e *bmc) /* TODO: i2c-8: Add BMC FRU eeprom@50 */ } =20 -static void ast2500_evb_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc =3D bmc->soc; - uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); - - smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, - eeprom_buf); - - /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), - TYPE_TMP105, 0x4d); -} - static void ast2600_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D bmc->soc; @@ -1176,23 +1152,6 @@ static void aspeed_machine_supermicrox11_bmc_class_i= nit(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } =20 -static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Aspeed AST2500 EVB (ARM1176)"; - amc->soc_name =3D "ast2500-a1"; - amc->hw_strap1 =3D AST2500_EVB_HW_STRAP1; - amc->fmc_model =3D "mx25l25635e"; - amc->spi_model =3D "mx25l25635f"; - amc->num_cs =3D 1; - amc->i2c_init =3D ast2500_evb_i2c_init; - mc->default_ram_size =3D 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, const void *data) { @@ -1546,10 +1505,6 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_supermicrox11_bmc_class_init, - }, { - .name =3D MACHINE_TYPE_NAME("ast2500-evb"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_ast2500_evb_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast2600-evb"), .parent =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c new file mode 100644 index 0000000000..4646c73e8e --- /dev/null +++ b/hw/arm/aspeed_ast2500_evb.c @@ -0,0 +1,66 @@ +/* + * ASPEED AST2500 EVB + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" +#include "hw/sensor/tmp105.h" + +/* AST2500 evb hardware value: 0xF100C2E6 */ +#define AST2500_EVB_HW_STRAP1 (( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_MAC1_RGMII | \ + SCU_HW_STRAP_MAC0_RGMII) & \ + ~SCU_HW_STRAP_2ND_BOOT_WDT) + +static void ast2500_evb_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, + eeprom_buf); + + /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), + TYPE_TMP105, 0x4d); +} + +static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Aspeed AST2500 EVB (ARM1176)"; + amc->soc_name =3D "ast2500-a1"; + amc->hw_strap1 =3D AST2500_EVB_HW_STRAP1; + amc->fmc_model =3D "mx25l25635e"; + amc->spi_model =3D "mx25l25635f"; + amc->num_cs =3D 1; + amc->i2c_init =3D ast2500_evb_i2c_init; + mc->default_ram_size =3D 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2500_evb_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("ast2500-evb"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_ast2500_evb_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_evb_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f788baabeb..cbee7ebf60 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', + 'aspeed_ast2500_evb.c', 'aspeed_ast2500_fp5280g2.c', 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_romulus.c', --=20 2.43.0