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Set it once in the callee. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20251010155045.78220-5-philmd@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++---------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 754cb80e22..7e69906e5b 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 + memop |=3D MO_TE; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 + memop |=3D MO_TE; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_load_inc(ctx, a, MO_SQ, false); } =20 static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_load_inc(ctx, a, MO_SQ, true); } =20 static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, false); + return gen_load_inc(ctx, a, MO_SL, false); } =20 static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, true); + return gen_load_inc(ctx, a, MO_SL, true); } =20 static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, false); + return gen_load_inc(ctx, a, MO_UL, false); } =20 static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, true); + return gen_load_inc(ctx, a, MO_UL, true); } =20 static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, false); + return gen_load_inc(ctx, a, MO_SW, false); } =20 static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, true); + return gen_load_inc(ctx, a, MO_SW, true); } =20 static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, false); + return gen_load_inc(ctx, a, MO_UW, false); } =20 static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, true); + return gen_load_inc(ctx, a, MO_UW, true); } =20 static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) @@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_store_inc(ctx, a, MO_SQ, false); } =20 static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_store_inc(ctx, a, MO_SQ, true); } =20 static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, false); + return gen_store_inc(ctx, a, MO_SL, false); } =20 static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, true); + return gen_store_inc(ctx, a, MO_SL, true); } =20 static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, false); + return gen_store_inc(ctx, a, MO_SW, false); } =20 static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, true); + return gen_store_inc(ctx, a, MO_SW, true); } =20 static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) --=20 2.51.0