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ACLINT and APLIC still assume a dense range, and if a hart is missing, this causes NULL derefs. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20251018154522.745788-2-djordje.todorovic@htecgroup.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 18 ++++++++++++++++-- hw/intc/riscv_aplic.c | 13 ++++++++++--- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 9f4c36e965..c6f13f647e 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -297,7 +297,12 @@ static void riscv_aclint_mtimer_realize(DeviceState *d= ev, Error **errp) s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); + CPUState *cpu_by_hartid =3D cpu_by_arch_id(s->hartid_base + i); + if (cpu_by_hartid =3D=3D NULL) { + /* Valid for sparse hart layouts - skip this hart ID */ + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_hartid); if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { error_report("MTIP already claimed"); exit(1); @@ -489,7 +494,12 @@ static void riscv_aclint_swi_realize(DeviceState *dev,= Error **errp) =20 /* Claim software interrupt bits */ for (i =3D 0; i < swi->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); + CPUState *cpu_by_hartid =3D cpu_by_arch_id(swi->hartid_base + i); + if (cpu_by_hartid =3D=3D NULL) { + /* Valid for sparse hart layouts - skip this hart ID */ + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_hartid); /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0)= { error_report("MSIP already claimed"); @@ -553,6 +563,10 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint= 32_t hartid_base, =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) { + /* Valid for sparse hart layouts - skip this hart ID */ + continue; + } RISCVCPU *rvcpu =3D RISCV_CPU(cpu); =20 qdev_connect_gpio_out(dev, i, diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 6dccca73af..a2041e7022 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -910,9 +910,12 @@ static void riscv_aplic_realize(DeviceState *dev, Erro= r **errp) if (!aplic->msimode) { /* Claim the CPU interrupt to be triggered by this APLIC */ for (i =3D 0; i < aplic->num_harts; i++) { - RISCVCPU *cpu; - - cpu =3D RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(aplic->hartid_base + i); + if (temp =3D=3D NULL) { + /* Valid for sparse hart layouts - skip this hart ID */ + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(temp); if (riscv_cpu_claim_interrupts(cpu, (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { error_report("%s already claimed", @@ -1095,6 +1098,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr = size, if (!msimode) { for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) { + /* Valid for sparse hart layouts - skip this hart ID */ + continue; + } =20 qdev_connect_gpio_out_named(dev, NULL, i, qdev_get_gpio_in(DEVICE(cpu), --=20 2.51.0